US-20260129961-A1 - SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

Abstract

A semiconductor device with low power consumption is provided. The semiconductor device includes a first layer and a second layer. The first layer includes a first cell and a first to a third circuit, and the second layer includes a second cell and a fourth and a fifth circuit. The first, second, and fourth circuits each have a function of converting digital data into analog current. The first cell calculates a product of a value from the first current and a value from the second circuit and inputs a calculation result into a third circuit as current. The third circuit generates analog current from the input current. The second cell calculates a product of a value from the third circuit and a value from the fourth circuit and inputs a calculation result into the fifth circuit as current. The fifth circuit generates analog current from the input current.

Inventors

• Yoshiyuki Kurokawa
• Satoru Ohshita
• Hidefumi Rikimaru

Assignees

• SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Dates

Publication Date

20260507

Application Date

20251223

Priority Date

20220516

Claims (1)

1. 1 . A semiconductor device comprising: a first layer comprising a first cell, a first circuit, a second circuit, and a third circuit; and a second layer comprising a second cell, a fourth circuit, and a fifth circuit, wherein the first layer is located below the second layer, wherein the first cell comprises a first transistor, wherein the second cell comprises a second transistor, wherein the first circuit is configured to convert a first data that is a digital data into a first analog current and configured to input the first analog current into the first cell, wherein the second circuit is configured to convert a second data that is a digital data into a second analog current and configured to input the second analog current into the first cell, wherein the fourth circuit is configured to convert a third data that is a digital data into a third analog current, wherein the first cell is configured to retain a first potential corresponding to the first analog current at a gate of the first transistor and configured to set a current flowing between a source and a drain of the first transistor to a first current corresponding to the first potential, wherein the second cell is configured to retain a third potential corresponding to the third analog current at a gate of the second transistor and configured to set a current flowing between a source and a drain of the second transistor to a third current corresponding to the third potential, wherein the second circuit is configured to change the first potential retained in the first cell into a second potential by inputting the second analog current into the first cell, wherein the first cell is configured to change the first current flowing between the source and the drain of the first transistor into a second current in accordance with the change of the first potential into the second potential, wherein the third circuit is configured to generate a fourth analog current corresponding to the second current and configured to input the fourth analog current into the second cell, so that the third potential retained in the second cell is changed into a fourth potential, wherein the second cell is configured to change the third current flowing between the source and the drain of the second transistor into a fourth current in accordance with the change of the third potential into the fourth potential, and wherein the fifth circuit is configured to generate a fifth analog current corresponding to the fourth current.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device and an electronic device. Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device (including a liquid crystal display device), a light-emitting device, a power storage device, an imaging device, a memory device, a signal processing device, a sensor, a processor, an electronic device, a system, a driving method thereof, a manufacturing method thereof, and a testing method thereof. 2. Description of the Related Art Integrated circuits that imitate the mechanism of the human brain are currently under active development. The integrated circuits incorporate electronic circuits as the brain mechanism and include circuits corresponding to neurons and synapses of the human brain. Such integrated circuits may therefore be referred to as “neuromorphic”, “brain-morphic”, or “brain-inspired” circuits. The integrated circuits have a non-von Neumann architecture and are expected to be able to perform parallel processing with extremely low power consumption as compared with a von Neumann architecture, which consumes higher power with increasing processing speed. An information processing model that imitates a biological neural network including neurons and synapses is referred to as an artificial neural network (ANN). By using an artificial neural network, inference with an accuracy as high as or higher than that of a human can be carried out. In an artificial neural network, the main arithmetic operation is the weighted sum operation of outputs from neurons, i.e., the product-sum operation. Non-Patent Document 1 proposes a product-sum operation circuit including a nonvolatile memory element. Each memory element of the product-sum operation circuit outputs current corresponding to a product of data corresponding to a multiplier stored in each memory element and input data corresponding to a multiplicand by using operation in a subthreshold region of a transistor containing silicon in its channel formation region. With the sum of currents output from the memory elements in each column, the product-sum operation circuit acquires data corresponding to product-sum operation. The product-sum operation circuit includes memory elements therein, and thus does not need to read and write data from and to an external memory when carrying out multiplication and addition. Such a product-sum operation circuit needs only a small number of times of data transfer for reading, writing, and the like, and thus is expected to achieve low power consumption. REFERENCE Non-Patent Document [Non-Patent Document 1]X. Guo et al., “Fast, Energy-Efficient, Robust, and Reproducible Mixed-Signal Neuromorphic Classifier Based on Embedded NOR Flash Memory Technology” IEDM2017, pp. 151-154. SUMMARY OF THE INVENTION The transistor characteristics and field-effect mobility of a transistor containing silicon in its channel formation region easily change due to a temperature change. In particular, when a product-sum operation circuit or the like is formed as an integrated circuit, the product-sum operation circuit operates to yield heat and the temperature of the integrated circuit rises, which makes characteristics of the transistors included in the integrated circuit change; thus, a normal arithmetic operation cannot be carried out in some cases. In the case where a digital circuit executes product-sum operation, a digital multiplier circuit executes multiplication of multiplier digital data (multiplier data) and multiplicand digital data (multiplicand data). After that, a digital adder circuit executes the addition of digital data yielded by the multiplication (product data), so that digital data (product-sum data) is obtained as the product-sum operation results. The digital multiplication circuit and the digital addition circuit preferably have specifications that allow a multi-bit arithmetic operation. This requires a large digital multiplication circuit and a large digital addition circuit, whereby the circuit area is likely to expand (leading to an increase in the circuit area) and the power consumption may increase. In a hierarchical artificial neural network model, for example, a product-sum operation and an arithmetic operation of a function system (e.g., a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold function) are performed in each layer of the hierarchy, in some cases. When calculation of the arti