US-20260129962-A1 - SEMICONDUCTOR DEVICE STRUCTURE INCLUDING FORKSHEET TRANSISTORS AND METHODS OF FORMING THE SAME

Abstract

A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, each first semiconductor layer has a first width, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall, each second semiconductor layer has a second width, a plurality of third semiconductor layers disposed adjacent the second side of the first dielectric wall, each third semiconductor layer has a third width greater than the second width, a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type.

Inventors

• Ta-Chun Lin
• Chih-Hung Hsieh
• Chun-Sheng Liang
• Wen-Chiang Hong
• Chun-Wing YEUNG
• Kuo-Hua Pan
• Chih-Hao Chang
• Jhon Jhy Liaw

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260507

Application Date

20260105

Claims (20)

1. 1 . A semiconductor device structure, comprising: a first dielectric wall; a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, each first semiconductor layer has a first width and two adjacent first semiconductor layers have a first space; a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall, each second semiconductor layer has a second width and two adjacent second semiconductor layers have a second space greater than the first space; a plurality of third semiconductor layers disposed adjacent the second side of the first dielectric wall, each third semiconductor layer has a third width greater than the second width; a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type; and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type.
2. 2 . The semiconductor device structure of claim 1 , wherein the second width is different than the first width.
3. 3 . The semiconductor device structure of claim 1 , wherein the second width is substantially identical to the first width.
4. 4 . The semiconductor device structure of claim 1 , wherein the third width is about 1.5 to about 10 times greater than the second width.
5. 5 . The semiconductor device structure of claim 1 , wherein the first dielectric wall has a wall width that is less than the first width or is less than the second width.
6. 6 . The semiconductor device structure of claim 1 , further comprising: an interfacial layer surrounding the at least three surfaces of each of the first semiconductor layers, the at least three surfaces of each of the second semiconductor layers, and at least three surfaces of each of the third semiconductor layers; and a high-k dielectric layer surrounding the interfacial layer.
7. 7 . The semiconductor device structure of claim 6 , wherein the interfacial layer disposed between the high-k dielectric layer and each of the first semiconductor layers has a first thickness, and the interfacial layer disposed between the high-k dielectric layer and each of the third semiconductor layers has a second thickness greater than the first thickness.
8. 8 . The semiconductor device structure of claim 1 , further comprising: a second dielectric wall disposed adjacent the first side of the first dielectric wall; a plurality of fourth semiconductor layers vertically stacked and extending outwardly from a first side of the second dielectric wall, each fourth semiconductor layer has a fourth width; and a plurality of fifth semiconductor layers vertically stacked and extending outwardly from a second side of the second dielectric wall, wherein the fifth semiconductor layers are disposed between the first semiconductor layers and the fourth semiconductor layers, and each fifth semiconductor layer has a fifth width.
9. 9 . The semiconductor device structure of claim 8 , wherein the fourth width is greater than the fifth width.
10. 10 . A semiconductor device structure, comprising: a first dielectric wall; a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, each first semiconductor layer has a first width; a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall, each second semiconductor layer has a second width; a plurality of third semiconductor layers disposed adjacent the second side of the first dielectric wall, each third semiconductor layer has a third width greater than the second width; an interfacial layer surrounding at least three surfaces of each of the first semiconductor layers, at least three surfaces of each of the second semiconductor layers, and at least three surfaces of each of the third semiconductor layers; a high-k dielectric layer surrounding the interfacial layer, wherein the interfacial layer disposed between the high-k dielectric layer and each of the first semiconductor layers has a first thickness, and the interfacial layer disposed between the high-k dielectric layer and each of the third semiconductor layers has a second thickness greater than the first thickness; a first gate electrode layer surrounding the at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type; and a second gate electrode layer surrounding the at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type.
11. 11 . The semiconductor device structure of claim 10 , wherein the second width is different than the first width.
12. 12 . The semiconductor device structure of claim 10 , wherein the second width is substantially identical to the first width.
13. 13 . The semiconductor device structure of claim 10 , wherein the third width is about 1.5 to about 10 times greater than the second width.
14. 14 . The semiconductor device structure of claim 10 , wherein the first dielectric wall has a wall width that is less than the first width or is less than the second width.
15. 15 . The semiconductor device structure of claim 10 , further comprising: a second dielectric wall disposed adjacent the first side of the first dielectric wall; a plurality of fourth semiconductor layers vertically stacked and extending outwardly from a first side of the second dielectric wall, each fourth semiconductor layer has a fourth width; and a plurality of fifth semiconductor layers vertically stacked and extending outwardly from a second side of the second dielectric wall, wherein the fifth semiconductor layers are disposed between the first semiconductor layers and the fourth semiconductor layers, and each fifth semiconductor layer has a fifth width.
16. 16 . The semiconductor device structure of claim 15 , wherein the fourth width is greater than the fifth width.
17. 17 . A semiconductor device structure, comprising: a first dielectric wall; a second dielectric wall disposed adjacent a first side of the first dielectric wall; a plurality of first semiconductor layers vertically stacked and extending outwardly from the first side of the first dielectric wall, each first semiconductor layer has a first width; a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall, each second semiconductor layer has a second width; a plurality of third semiconductor layers disposed adjacent the second side of the first dielectric wall, each third semiconductor layer has a third width greater than the second width; a plurality of fourth semiconductor layers vertically stacked and extending outwardly from a first side of the second dielectric wall, each fourth semiconductor layer has a fourth width; a plurality of fifth semiconductor layers vertically stacked and extending outwardly from a second side of the second dielectric wall, wherein the fifth semiconductor layers are disposed between the first semiconductor layers and the fourth semiconductor layers, and each fifth semiconductor layer has a fifth width, wherein the fourth width is greater than the fifth width; a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type; and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type.
18. 18 . The semiconductor device structure of claim 17 , wherein the second width is different than the first width.
19. 19 . The semiconductor device structure of claim 17 , wherein the second width is substantially identical to the first width.
20. 20 . The semiconductor device structure of claim 17 , wherein the third width is about 1.5 to about 10 times greater than the second width.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. Non-Provisional application Ser. No. 18/097,263, filed Jan. 15, 2023, which claims priority to U.S. Provisional Application Ser. No. 63/414,535, filed Oct. 9, 2022. U.S. Non-Provisional application Ser. No. 18/097,263 and U.S. Provisional Application Ser. No. 63/414,535 are incorporated by reference in their entireties. BACKGROUND The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down presents new challenge. For example, transistors using nanowire channels have been proposed to achieve increased device density, greater carrier mobility and drive current in a device. As device size reduces, there is a continuous need to improve processing and manufacturing ICs. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1-2 are perspective views of various stages of manufacturing a semiconductor device structure, in accordance with some embodiments. FIG. 3A-14A are cross-sectional side views of various stages of manufacturing the semiconductor device structure taken along line A-A of FIG. 3C, in accordance with some embodiments. FIG. 3B-14B are cross-sectional side views of various stages of manufacturing the semiconductor device structure taken along line B-B of FIG. 3C, in accordance with some embodiments. FIG. 3C-14C are top views of the semiconductor device structure of FIG. 2 in accordance with some embodiments. FIG. 9 is a perspective view of one of the various stages of manufacturing the semiconductor device structure, in accordance with some embodiments. FIG. 15-18 are cross-sectional views of various stages of manufacturing the semiconductor device structure of FIG. 14A in accordance with some embodiments. FIG. 18-1 illustrates a cross-sectional view of the semiconductor device structure in accordance with some embodiments. FIG. 19-26 are top-views of a semiconductor device structure, in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “on,” “top,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. While the embodiments of this disclosure are discussed with respect to nanosheet channel FETs, implementations of some aspects of the present disclosure may be used in other processes and/or in other devices, such as planar FETs, Fin-FETs, Horizontal Gate All Around (HGAA) FETs, Vertical Gate All Around (VGAA) FETs, and other suitable devices. A person having ordinary skill in the art will readily understand other modifications that may be made are contemplated within