US-20260129965-A1 - SEMICONDUCTOR DEVICE WITH I/O DEVICE AT GATE MODULE

Abstract

A semiconductor device includes an input/output device including: a top transistor having a top source region and top drain region and a bottom transistor comprising a bottom source region and a bottom drain region. The top source region is located over the bottom drain region, the top drain region is located over the bottom source region, the top source region is isolated from contact with the bottom drain region, and the top drain region is connected to the bottom source region.

Inventors

• Paul Charles Jamison
• Takashi Ando
• Shay REBOH
• Junli Wang
• Debarghya Sarkar
• Abir Shadman

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260507

Application Date

20241101

Claims (20)

1. 1 . A semiconductor device, comprising: an input/output device comprising: a top transistor comprising a top source region and top drain region; and a bottom transistor comprising a bottom source region and a bottom drain region, wherein: the top source region is located over the bottom drain region, the top drain region is located over the bottom source region, the top source region is isolated from contact with the bottom drain region, and the top drain region is connected to the bottom source region.
2. 2 . The semiconductor device of claim 1 , wherein the top transistor and the bottom transistor are field-effect transistors.
3. 3 . The semiconductor device of claim 1 , wherein the top transistor and the bottom transistor are doped with a P-type dopant.
4. 4 . The semiconductor device of claim 1 , wherein the top transistor and the bottom transistor are doped with an N-type dopant.
5. 5 . The semiconductor device of claim 1 , further comprising: a top set of nanosheet gates horizontally extended between the top source region and the top drain region, and a bottom set of nanosheet gates horizontally extended between the bottom source region and the bottom drain region.
6. 6 . The semiconductor device of claim 1 , wherein the top drain region and the bottom source region are configured to serially connect the top transistor to the bottom transistor.
7. 7 . The semiconductor device of claim 1 , further comprising a logic device connected to the input/output device.
8. 8 . A method of fabricating a semiconductor device, the method comprising: forming a stacked input/output device comprising: forming a top transistor by forming a top source region and top drain region; and forming a bottom transistor by forming a bottom source region and a bottom drain region, wherein: the top source region is located over the bottom drain region, the top drain region is located over the bottom source region, the top source region is isolated from contact with the bottom drain region, and the top drain region is connected to the bottom source region.
9. 9 . The method of claim 8 , wherein the top transistor and the bottom transistor are field-effect transistors.
10. 10 . The method of claim 8 , further comprising: doping the top transistor and the bottom transistor with a P-type dopant.
11. 11 . The method of claim 8 , further comprising doping the top transistor and the bottom transistor with an N-type dopant.
12. 12 . The method of claim 8 , further comprising: forming a top set of nanosheet gates horizontally extended between the top source region and the top drain region, and forming a bottom set of nanosheet gates horizontally extended between the bottom source region and the bottom drain region.
13. 13 . The method of claim 8 , further comprising forming a serially connected top transistor and bottom transistor by connecting the top drain region and the bottom source region.
14. 14 . The method of claim 8 , further comprising forming a logic device connected to the stacked input/output device.
15. 15 . A semiconductor device, comprising: an input/output device comprising: a top transistor comprising a top source region and top drain region; and a bottom transistor comprising a bottom source region and a bottom drain region, wherein the top transistor and the bottom transistor are doped with a same dopant.
16. 16 . The semiconductor device of claim 15 , wherein: the top source region is located over the bottom drain region, the top drain region is located over the bottom source region, the top source region is isolated from contact with the bottom drain region, and the top drain region is connected to the bottom source region.
17. 17 . The semiconductor device of claim 15 , wherein the top transistor and the bottom transistor are field-effect transistors.
18. 18 . The semiconductor device of claim 15 , wherein the dopant is a P-type dopant or an N-type dopant.
19. 19 . The semiconductor device of claim 15 , further comprising: a top set of nanosheet gates horizontally extended between the top source region and the top drain region, and a bottom set of nanosheet gates horizontally extended between the bottom source region and the bottom drain region.
20. 20 . The semiconductor device of claim 15 , further comprising a logic device connected to the input/output device, and wherein the top drain region and the bottom source region are configured to serially connect the top transistor to the bottom transistor.

Description

BACKGROUND Technical Field The present disclosure generally relates to semiconductors, and more particularly, to semiconductors with I/O device at gate module structure, and methods of creation thereof. Description of Related Art The continuous miniaturization of transistors and their increasing density on chips are hallmark innovations in the semiconductor industry, closely following Moore's Law. This trend has enabled transistors to shrink to nanometer scales, allowing millions, and even billions, to be integrated onto a single chip. This advancement significantly boosts computational power and energy efficiency. The evolution towards system-on-chip architectures further enhances these capabilities by integrating various functionalities, such as processing and sensing, into a single chip. SUMMARY According to an embodiment, a semiconductor device includes an input/output device having a top transistor comprising a top source region and top drain region; and a bottom transistor comprising a bottom source region and a bottom drain region. The top source region is located over the bottom drain region, the top drain region is located over the bottom source region, the top source region is isolated from contact with the bottom drain region, and the top drain region is connected to the bottom source region. In one embodiment, the top transistor and the bottom transistor are field-effect transistors. In one embodiment, the top transistor and the bottom transistor are doped with a P-type dopant. In one embodiment, the top transistor and the bottom transistor are doped with an N-type dopant. In one embodiment, the semiconductor device includes a top set of nanosheet gates horizontally extended between the top source region and the top drain region, and a bottom set of nanosheet gates horizontally extended between the bottom source region and the bottom drain region. In one embodiment, the top drain region and the bottom source region are configured to serially connect the top transistor to the bottom transistor. In one embodiment, the semiconductor device includes a logic device connected to the input/output device. According to an embodiment, a method of fabricating a semiconductor device includes forming a stacked input/output device having a top transistor by forming a top source region and top drain region, and a bottom transistor by forming a bottom source region and a bottom drain region. The top source region is located over the bottom drain region, the top drain region is located over the bottom source region, the top source region is isolated from contact with the bottom drain region, and the top drain region is connected to the bottom source region. In one embodiment, the top transistor and the bottom transistor are field-effect transistors. In one embodiment, the method includes doping the top transistor and the bottom transistor with a P-type dopant. In one embodiment, the method includes doping the top transistor and the bottom transistor with an N-type dopant. In one embodiment, the method includes forming a top set of nanosheet gates horizontally extended between the top source region and the top drain region, and forming a bottom set of nanosheet gates horizontally extended between the bottom source region and the bottom drain region. In one embodiment, the method includes forming a serially connected top transistor and bottom transistor by connecting the top drain region and the bottom source region. In one embodiment, the method includes forming a logic device connected to the input/output device. According to an embodiment, a semiconductor device includes an input/output device having a top transistor comprising a top source region and top drain region and a bottom transistor comprising a bottom source region and a bottom drain region. The top transistor and the bottom transistor are doped with a same dopant. In one embodiment, the top source region is located over the bottom drain region, the top drain region is located over the bottom source region, the top source region is isolated from contact with the bottom drain region, and the top drain region is connected to the bottom source region. In one embodiment, the top transistor and the bottom transistor are field-effect transistors. In one embodiment, the dopant is a P-type dopant or an N-type dopant. In one embodiment, the semiconductor device includes a top set of nanosheet gates horizontally extended between the top source region and the top drain region, and a bottom set of nanosheet gates horizontally extended between the bottom source region and the bottom drain region. In one embodiment, the semiconductor device includes a logic device connected to the input/output device, and the top drain region and the bottom source region are configured to serially connect the top transistor to the bottom transistor. These and other features will become apparent from the following detailed description of illustrative embodiments thereof, which is to