US-20260129966-A1 - SHIFTED STACKED FETS

Abstract

A semiconductor device includes a first transistor in a first stacked level and a second transistor in a second stacked level. A first active region of the first transistor is shifted with respect to a second active region of the second transistor. A first dielectric bar confines the first active region on one side. A second dielectric bar confines the second active region on one side, wherein the first dielectric bar is on an opposite side of the second dielectric bar.

Inventors

• Debarghya Sarkar
• Ruilong Xie
• Julien Frougier
• Huimei Zhou
• Shogo Mochizuki

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260507

Application Date

20241104

Claims (20)

1. 1 . A semiconductor device, comprising: a first transistor in a first stacked level; a second transistor in a second stacked level; a first active region of the first transistor shifted with respect to a second active region of the second transistor; a first dielectric bar confining the first active region on one side; and a second dielectric bar confining the second active region on one side, wherein the first dielectric bar is on an opposite side of the second dielectric bar relative to corresponding active regions.
2. 2 . The semiconductor device of claim 1 , further comprising a frontside deep contact extending through the first stacked level to connect with the second active region.
3. 3 . The semiconductor device of claim 1 , further comprising a backside deep contact extending through the second stacked level to connect with the first active region.
4. 4 . The semiconductor device of claim 1 , wherein adjacent first dielectric bars bound a wiring channel that permits passage of contacts, with electrical isolation, past the first active region.
5. 5 . The semiconductor device of claim 1 , wherein adjacent second dielectric bars bound a wiring channel that permits passage of contacts, with electrical isolation, past the second active region.
6. 6 . The semiconductor device of claim 1 , further comprising backside power rails formed on a backside of the semiconductor device and electrically connected to at least one of the first active region and the second active region.
7. 7 . A semiconductor device, comprising: a first transistor level including first source/drain regions; and a second transistor level including second source/drain regions, the second transistor level being stacked over the first transistor level; wherein the first source/drain regions are shifted with respect to the second source/drain regions; and wherein the first source/drain regions are confined on one side by first dielectric bars and the second source/drain regions are confined on one side by second dielectric bars, the first dielectric bars being on an opposite side of the second dielectric bars relative to respective source/drain regions.
8. 8 . The semiconductor device of claim 7 , further comprising a frontside deep contact extending through the first transistor level to connect with a second source/drain region.
9. 9 . The semiconductor device of claim 7 , further comprising a backside deep contact extending through the second transistor level to connect with a first source/drain region.
10. 10 . The semiconductor device of claim 7 , wherein adjacent first dielectric bars bound a wiring channel that permits passage of contacts, with electrical isolation, past a first source/drain region.
11. 11 . The semiconductor device of claim 7 , wherein adjacent second dielectric bars bound a wiring channel that permits passage of contacts, with electrical isolation, past a second source/drain region.
12. 12 . The semiconductor device of claim 7 , further comprising backside power rails formed on a backside of the semiconductor device and electrically connected to at least one source/drain region.
13. 13 . The semiconductor device of claim 7 , wherein the first source/drain regions and first dielectric bars follow a first alternating pattern in the first transistor level.
14. 14 . The semiconductor device of claim 13 , wherein the second source/drain regions and second dielectric bars follow a second alternating pattern in the second transistor level.
15. 15 . The semiconductor device of claim 14 , wherein the first alternating pattern and the second alternating pattern are offset from each other.
16. 16 . The semiconductor device of claim 7 , further comprising gate structures formed on the first transistor level and in the second transistor level, the gate structures including a shared connection between the gate structures of the first transistor level and the gate structures of the second transistor level.
17. 17 . The semiconductor device of claim 16 , wherein the gate structures in the first transistor level include gate electrodes that encapsulate the first dielectric bars.
18. 18 . A semiconductor device, comprising: first transistors in a first stacked level; second transistors in a second stacked level; first source/drain regions of the first transistors being shifted with respect to second source/drain regions of the second transistors; wherein the first source/drain regions are confined on one side by first dielectric bars and the second source/drain regions are confined on one side by second dielectric bars, the first dielectric bars being on an opposite side of the second dielectric bars relative to respective source/drain regions; and wiring channels on one stacked level being aligned with unconfined sides of source/drain regions on an adjacent stacked level.
19. 19 . The semiconductor device of claim 18 , wherein the wiring channels are bound by first dielectric bars on one stacked level and the second dielectric bars on another stacked level.
20. 20 . The semiconductor device of claim 19 , further comprising a deep contact extending through one stacked level through a wiring channel to connect with a source/drain region on another stacked level.

Description

BACKGROUND The present invention generally relates to semiconductor devices and processing methods, and more particularly to stacked field effect transistors (FETs) shifted between stacked layers to reduce layout area needed for contacts. Stacked transistor devices may be used to increase areal density of devices on a chip. Additionally, the close proximity of the overlying and underlying devices can be useful when forming paired devices, such as complementary semiconductor devices that include two devices of opposing polarity. However, positioning transistors above one another places spatial and electrical constraints that can make it challenging to provide required performance. An electrical constraint arises when attempting to connect to source/drain regions on different stack levels. Areal space is needed for contacts that bypass one level and connect to another level. The areal space for the contacts needs to account for adequate conduction of the contact and adequate dielectric protection around the contacts to prevent short circuits. Therefore, a need exists for wiring patterns that can connect to source/drain regions on different stack levels while minimizing consumed layout area. SUMMARY In accordance with an embodiment of the present invention, a semiconductor device includes a first transistor in a first stacked level and a second transistor in a second stacked level. A first active region of the first transistor is shifted with respect to a second active region of the second transistor. A first dielectric bar confines the first active region on one side. A second dielectric bar confines the second active region on one side, wherein the first dielectric bar is on an opposite side of the second dielectric bar. In other embodiments, a frontside deep contact can extend through the first stacked level to connect with the second active region. A backside deep contact can extend through the second stacked level to connect with the first active region. Adjacent first dielectric bars can bound a wiring channel that permits passage of contacts, with electrical isolation, past the first active region. Adjacent second dielectric bars can bound a wiring channel that permits passage of contacts, with electrical isolation, past the second active region. Backside power rails can be formed on a backside of the semiconductor device and electrically connected to at least one of the first active region and the second active region. In accordance with another embodiment of the present invention, a semiconductor device, includes a first transistor level including first source/drain regions and a second transistor level including second source/drain regions, the second transistor level being stacked over the first transistor level. The first source/drain regions are shifted with respect to the second source/drain regions, and the first source/drain regions are confined on one side by first dielectric bars and the second source/drain regions are confined on one side by second dielectric bars. The first dielectric bars are on an opposite side of the second dielectric bars relative to respective source/drain regions. In other embodiments, a frontside deep contact can extend through the first transistor level to connect with a second source/drain region. A backside deep contact can extend through the second transistor level to connect with a first source/drain region. Adjacent first dielectric bars can bound a wiring channel that permits passage of contacts, with electrical isolation, past a first source/drain region. Adjacent second dielectric bars can bound a wiring channel that permits passage of contacts, with electrical isolation, past a second source/drain region. Backside power rails can be formed on a backside of the semiconductor device and electrically connected to at least one source/drain region. The first source/drain regions and first dielectric bars can follow a first alternating pattern in the first transistor level. The second source/drain regions and second dielectric bars can follow a second alternating pattern in the second transistor level. The first alternating pattern and the second alternating pattern can be offset from each other. Gate structures can be formed on the first transistor level and on the second transistor level, the gate structures including a shared connection between the gate structures of the first transistor level and the gate structures of the second transistor level. The gate structures at the first transistor level (and/or second transistor level) can include gate electrodes that encapsulate the first dielectric bars. In accordance with another embodiment of the present invention, a semiconductor device includes first transistors in a first stacked level and second transistors in a second stacked level. First source/drain regions of the first transistors are shifted with respect to second source/drain regions of the second transistors, wherein the first source/drain regions are