US-20260129967-A1 - LOW CAPACITANCE AND MULTI-THRESHOLD VOLTAGE NANOSHEET DEVICE

Abstract

A semiconductor device including nanosheets transistors that have low capacitance and different threshold voltages is provided. The different threshold voltage are obtained using different shaped semiconductor channel material nanosheets and, in some embodiments, by providing different dopant concentrations to the high-k gate dielectric layers of the nanosheet transistors.

Inventors

• Xiaoli He
• Ruilong Xie
• Takashi Ando
• Kishwar Mashooq
• Julien Frougier

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260507

Application Date

20241107

Claims (20)

1. 1 . A semiconductor device comprising: a first nanosheet transistor comprising a first nanosheet stack of semiconductor channel material nanosheets having a first thickness located beneath a suspended portion of each of the semiconductor channel material nanosheets, and a first gate structure comprising a first metal doped high-k gate dielectric layer having a first metal dopant concentration wrapped around the suspended portion of each first semiconductor channel material nanosheet; and a second nanosheet transistor comprising a second nanosheet stack of dog-bone shaped nanosheets having a second thickness located beneath a suspended portion of each of the dog-bone shaped nanosheets, and a second gate structure comprising a second metal doped high-k gate dielectric layer having a second metal dopant concentration wrapped around the suspended portion of each of the dog-bone shaped nanosheets, wherein the second thickness is greater than the first thickness.
2. 2 . The semiconductor device of claim 1 , wherein the second metal dopant concentration is less than the first metal dopant concentration.
3. 3 . The semiconductor device of claim 1 , wherein the second metal dopant concentration is equal to the first metal dopant concentration.
4. 4 . The semiconductor device of claim 1 , wherein the first nanosheet transistor has a first threshold voltage and the second nanosheet transistor has a second threshold voltage in which second threshold voltage is greater than the first threshold voltage.
5. 5 . The semiconductor device of claim 1 , wherein the first metal doped high-k gate dielectric layer and the second metal doped high-k gate dielectric layer comprise a Group 2 metal.
6. 6 . The semiconductor device of claim 1 , wherein the first metal doped high-k gate dielectric layer and the second metal doped high-k gate dielectric layer comprise a Group 3 metal.
7. 7 . The semiconductor device of claim 1 , wherein the first metal doped high-k gate dielectric layer and the second metal doped high-k gate dielectric layer comprise a Group 4 metal.
8. 8 . The semiconductor device of claim 1 , wherein the first metal doped high-k gate dielectric layer and the second metal doped high-k gate dielectric layer comprise a Group 13 metal.
9. 9 . The semiconductor device of claim 1 , wherein the first gate structure and the second gate structure further include a gate electrode, wherein the gate electrode comprises at least a work function metal.
10. 10 . The semiconductor device of claim 1 , further comprising a semiconductor substrate located beneath the first nanosheet transistor and the second nanosheet transistor, and wherein the first metal doped high-k gate dielectric layer and the second metal doped high-k gate dielectric layer are present on the semiconductor substrate.
11. 11 . The semiconductor device of claim 10 , further comprises a shallow trench isolation structure located in an upper portion of the semiconductor substrate, and wherein the first metal doped high-k gate dielectric layer and the second metal doped high-k gate dielectric layer are present on the shallow trench isolation structure.
12. 12 . The semiconductor device of claim 1 , wherein the first thickness is equal to or less than 7 nm.
13. 13 . A semiconductor device comprising: a first nanosheet transistor having a first threshold voltage Vt 1 , and comprising a first high-k gate dielectric layer having a first metal doping concentration C 1 ; a second nanosheet transistor having a second threshold voltage Vt 2 , and comprising a second high-k gate dielectric layer having a second metal doping concentration C 2 ; a third nanosheet transistor having a third threshold voltage Vt 3 , and comprising a third high-k gate dielectric layer having a third metal doping concentration C 4 ; and a fourth nanosheet transistor having a fourth threshold voltage Vt 4 , and comprising a fourth high-k gate dielectric layer having a fourth metal doping concentration C 4 , wherein the first nanosheet transistor and the third nanosheet transistor further comprise a first nanosheet stack of semiconductor channel material nanosheets having a first thickness located beneath a suspended portion of each of the semiconductor channel material nanosheets, and the second nanosheet transistor and the fourth nanosheet transistor further comprise a second nanosheet stack of dog-bone shaped nanosheets having a second thickness located beneath a suspended portion of each of the dog-bone shaped nanosheets, wherein the second thickness is greater than the first thickness, C 1 =C 2 , C 3 =C 4 , and C 1 and C 2 are greater than C 3 and C 4 , and Vt 1 <Vt 2 <Vt 3 <Vt 4 .
14. 14 . The semiconductor device of claim 13 , further comprising: a fifth nanosheet transistor having a fifth threshold voltage Vt 5 , and comprising a fifth high-k gate dielectric layer; and a sixth nanosheet transistor having a sixth threshold voltage Vt 6 and comprising a sixth high-k gate dielectric layer, wherein the fifth high-k gate dielectric layer and the sixth high-k gate dielectric layer are devoid of a metal dopant, and the fifth nanosheet transistor further comprises the first nanosheet stack and the sixth nanosheet transistor further comprises the second nanosheet stack and wherein Vt 1 <Vt 2 <Vt 3 <Vt 4 <Vt 5 <Vt 6 .
15. 15 . The semiconductor device of claim 13 , wherein the first high-k gate dielectric layer, the second high-k gate dielectric layer, the third high-k gate dielectric layer and the fourth high-k gate dielectric layer comprise a high-k gate dielectric and a Group 2 metal.
16. 16 . The semiconductor device of claim 13 , wherein the first high-k gate dielectric layer, the second high-k gate dielectric layer, the third high-k gate dielectric layer and the fourth high-k gate dielectric layer comprise a high-k gate dielectric and a Group 3 metal.
17. 17 . The semiconductor device of claim 13 , wherein the first high-k gate dielectric layer, the second high-k gate dielectric layer, the third high-k gate dielectric layer and the fourth high-k gate dielectric layer comprise a high-k gate dielectric and a Group 4 metal.
18. 18 . The semiconductor device of claim 13 , wherein the first high-k gate dielectric layer, the second high-k gate dielectric layer, the third high-k gate dielectric layer and the fourth high-k gate dielectric layer comprise a high-k gate dielectric and a Group 13 metal.
19. 19 . The semiconductor device of claim 13 , wherein the first nanosheet transistor, the second nanosheet transistor, the third nanosheet transistor and the fourth nanosheet transistor further comprises a gate electrode, wherein the gate electrode comprises a work function metal.
20. 20 . The semiconductor device of claim 13 , further comprising a semiconductor substrate located beneath the first nanosheet transistor, the second nanosheet transistor, the third nanosheet transistor and the fourth nanosheet transistor, and wherein each of the first high-k gate dielectric layer, the second high-k gate dielectric layer, the third high-k gate dielectric layer and the fourth high-k gate dielectric layer is present on the semiconductor substrate.

Description

BACKGROUND The present application relates to semiconductor technology, and more particularly to a semiconductor device including nanosheets transistors that have low capacitance and different threshold voltages. The use of non-planar semiconductor transistors is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. One type of non-planar semiconductor transistor that has been touted as a viable option beyond the 7 nm technology node is a nanosheet transistor. By “nanosheet transistor” it is meant that a device contains one or more semiconductor channel material nanosheets that are stacked one over the other, in which a gate structure is formed in a wrap-around manner around a suspended portion of the one or more semiconductor channel material nanosheets. Due to this wrap around nature, nanosheet transistors are oftentimes referred to as a gate-all-around (GAA) transistors. Nanosheet transistors provide considerable scaling with high drive current capability. Further, nanosheet transistors provide a larger drive current for a given footprint compared to finFET technology. SUMMARY A semiconductor device including nanosheets transistors that have low capacitance and different threshold voltages is provided. The different threshold voltage are obtained using different shaped semiconductor channel material nanosheets and, in some embodiments, by providing different dopant concentrations to the high-k gate dielectric layers of the nanosheet transistors. In one embodiment of the present application, the semiconductor device includes a first nanosheet transistor including a first nanosheet stack of semiconductor channel material nanosheets having a first thickness (i.e., Tsus1) located beneath a suspended portion of each of the semiconductor channel material nanosheets, and a first gate structure including a first metal doped high-k gate dielectric layer having a first metal dopant concentration wrapped around the suspended portion of each first semiconductor channel material nanosheet. The semiconductor device further includes a second nanosheet transistor that includes a second nanosheet stack of dog-bone shaped nanosheets having a second thickness (i.e., Tsus2) located beneath a suspended portion of each of the dog-bone shaped nanosheets, and a second gate structure including a second metal doped high-k gate dielectric layer having a second metal dopant concentration wrapped around the suspended portion of each of the dog-bone shaped nanosheets. In accordance with the present application, the second thickness is greater than the first thickness. In another embodiment of the present application, the semiconductor device includes a first nanosheet transistor having a first threshold voltage Vt1, and including a first high-k gate dielectric layer having a first metal doping concentration C1; a second nanosheet transistor having a second threshold voltage Vt2, and including a second high-k gate dielectric layer having a second metal doping concentration C2; a third nanosheet transistor having a third threshold voltage Vt3, and including a third high-k gate dielectric layer having a third metal doping concentration C3; and a fourth nanosheet transistor having a fourth threshold voltage Vt4, and including a fourth high-k gate dielectric layer having a fourth metal doping concentration C4. In this embodiment of the present application, the first nanosheet transistor and the third nanosheet transistor further include a first nanosheet stack of semiconductor channel material nanosheets having a first thickness located beneath a suspended portion of each of the semiconductor channel material nanosheets, and the second nanosheet transistor and the fourth nanosheet transistor further include a second nanosheet stack of dog-bone shaped nanosheets having a second thickness located beneath a suspended portion of each of the dog-bone shaped nanosheets in which the second thickness is greater than the first thickness, and C1=C2, C3=C4, and C1 and 2 is greater than C3 and C4. In this embodiment of the present disclosure, Vt1<Vt2<Vt3<Vt4. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a top down view illustrating a device layout that can be used in accordance with an embodiment of the present application. FIG. 2A is a cross sectional view of a first exemplary structure along cut X-X shown in FIG. 1 that can be used in forming a low threshold voltage semiconductor device, the first exemplary structure including a first patterned material stack of sacrificial semiconductor material layers and semiconductor channel material layers located on a semiconductor substrate. FIG. 2B is a cross sectional view of the first exemplary structure along cut Y1-Y1 shown in FIG. 1 that can be used in forming the low threshold voltage semiconductor device. FIG. 3A is a cross sectional view of a second exemplary structure along cut X-X shown in FIG. 1 that can be used in forming a high threshold voltage semiconductor