US-20260129968-A1 - TRANSISTOR GATE STRUCTURES AND METHODS OF FORMING THE SAME

US20260129968A1US 20260129968 A1US20260129968 A1US 20260129968A1US-20260129968-A1

Abstract

In an embodiment, a device includes: an isolation region on a substrate; a first semiconductor fin protruding above the isolation region; a first gate dielectric on a first channel region of the first semiconductor fin, the first gate dielectric including a first interfacial layer and a first high-k dielectric layer; a second semiconductor fin protruding above the isolation region; and a second gate dielectric on a second channel region of the second semiconductor fin, the second gate dielectric including a second interfacial layer and a second high-k dielectric layer, a first portion of the first interfacial layer on the first channel region having a greater thickness than a second portion of the second interfacial layer on the second channel region, the second channel region having a greater height than the first channel region.

Inventors

Hsueh-Ju CHEN
Yi Hsuan Chen
Jyun-Yi Wu
Wen-Hung Huang
Tsung-Da Lin
Jian-Hao Chen
Cheng-Lung Hung
Kuo-Feng Yu

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20251229

Claims (20)

1 . A device comprising: an isolation region on a substrate; a first semiconductor fin protruding above the isolation region; a first gate dielectric on a first channel region of the first semiconductor fin, the first gate dielectric comprising a first interfacial layer and a first high-k dielectric layer; a second semiconductor fin protruding above the isolation region; and a second gate dielectric on a second channel region of the second semiconductor fin, the second gate dielectric comprising a second interfacial layer and a second high-k dielectric layer, a first portion of the first interfacial layer on the first channel region having a greater thickness than a second portion of the second interfacial layer on the second channel region, the second channel region having a greater height than the first channel region.
2 . The device of claim 1 , wherein the first gate dielectric and the second gate dielectric are each disposed on the isolation region, and a third portion of the first interfacial layer on the isolation region has the same thickness as a fourth portion of the second interfacial layer on the isolation region.
3 . The device of claim 1 , wherein a first top surface of the first channel region is substantially flat, and a second top surface of the second channel region is substantially flat.
4 . The device of claim 1 , wherein a first top surface of the first channel region is convex, and a second top surface of the second channel region is substantially flat.
5 . The device of claim 1 , wherein a side of the first semiconductor fin comprises a first sidewall, a second sidewall, and an indented stairstep surface, the indented stairstep surface connecting the first sidewall to the second sidewall, the first interfacial layer extending along the first sidewall, the second sidewall, and the indented stairstep surface.
6 . The device of claim 1 , further comprising: a first gate electrode on the first gate dielectric; and a second gate electrode on the second gate dielectric, the first gate electrode having a greater width than the second gate electrode.
7 . A device comprising: a first semiconductor fin extending from a substrate, a side of the first semiconductor fin comprising a first sidewall, a second sidewall, and an indented stairstep surface, the indented stairstep surface connecting the first sidewall to the second sidewall; a first gate dielectric comprising a first interfacial layer extending along the first sidewall, the second sidewall, and the indented stairstep surface of the first semiconductor fin; a second semiconductor fin extending from the substrate, a side of the second semiconductor fin comprising a single sidewall; and a second gate dielectric comprising a second interfacial layer extending along the single sidewall of the second semiconductor fin.
8 . The device of claim 7 , wherein the indented stairstep surface is substantially flat.
9 . The device of claim 7 , wherein the indented stairstep surface is convex.
10 . The device of claim 7 , wherein the first gate dielectric is disposed on a first channel region of the first semiconductor fin, the second gate dielectric is disposed on a second channel region of the second semiconductor fin, and the second channel region has a greater height than the first channel region.
11 . The device of claim 7 , further comprising: a first gate electrode on the first gate dielectric; and a second gate electrode on the second gate dielectric, the first gate electrode having a greater width than the second gate electrode.
12 . The device of claim 7 , further comprising: an isolation region on the substrate, the isolation region extending along the first sidewall of the first semiconductor fin and along the single sidewall of the second semiconductor fin.
13 . The device of claim 7 , wherein a first portion of the first interfacial layer extending along the first sidewall has a greater thickness than a second portion of the second interfacial layer extending along the single sidewall.
14 . The device of claim 13 , further comprising: an isolation region on the substrate, wherein the first interfacial layer and the second interfacial layer each extend along a top surface of the isolation region, wherein a third portion of the first interfacial layer extending along the top surface of the isolation region has the same thickness as a fourth portion of the second interfacial layer extending along the top surface of the isolation region.
15 . The device of claim 7 , wherein a top surface of a first channel region of the first semiconductor fin has a different shape than a top surface of a second channel region of the second semiconductor fin.
16 . A device comprising: an isolation region on a substrate; a first semiconductor fin protruding above a top surface of the isolation region, a first side of the first semiconductor fin comprising a first sidewall, a second sidewall, and an indented stairstep surface connecting the first sidewall to the second sidewall, the isolation region extending along the first sidewall; a first gate dielectric comprising a first interfacial layer extending along the second sidewall of the first semiconductor fin, the indented stairstep surface of the first semiconductor fin, and the top surface of the isolation region; a second semiconductor fin protruding above the isolation region, a second side of the second semiconductor fin comprising a single sidewall, the isolation region extending along the single sidewall; and a second gate dielectric comprising a second interfacial layer extending along the single sidewall of the second semiconductor fin and the top surface of the isolation region, wherein a first portion of the first interfacial layer extending along the second sidewall of the first semiconductor fin has a greater thickness than a second portion of the second interfacial layer extending along the single sidewall of the second semiconductor fin.
17 . The device of claim 16 , wherein a third portion of the first interfacial layer extending along the top surface of the isolation region has the same thickness as a fourth portion of the second interfacial layer extending along the top surface of the isolation region.
18 . The device of claim 16 , wherein a first channel region of the first semiconductor fin has a greater length than a second channel region of the second semiconductor fin, and the second channel region of the second semiconductor fin has a greater height than the first channel region of the first semiconductor fin.
19 . The device of claim 16 , wherein the indented stairstep surface is substantially flat and substantially parallel to a major surface of the substrate.
20 . The device of claim 16 , wherein the indented stairstep surface is convex.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This application is a division of U.S. patent application Ser. No. 17/703,329, filed on Mar. 24, 2022, which claims the benefit of U.S. Provisional Application No. 63/264,388, filed on Nov. 22, 2021, which applications are hereby incorporated herein by reference. BACKGROUND Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. However, as the minimum features sizes are reduced, additional problems arise that should be addressed. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates an example of Fin Field-Effect Transistors (FinFETs), in accordance with some embodiments. FIGS. 2-19B are views of intermediate stages in the manufacturing of FinFETs, in accordance with some embodiments. FIG. 20 is a view of FinFETs, in accordance with some embodiments. FIG. 21 is a view of FinFETs, in accordance with some embodiments. FIG. 22 is a view of FinFETs, in accordance with some embodiments. FIG. 23 is a view of FinFETs, in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. According to various embodiments, dummy gate dielectrics are removed during a gate replacement process, and replacement interfacial layers are formed in their place. The dummy gate dielectrics are thus not used as interfacial layers in subsequently formed replacement gates. The replacement interfacial layers may be higher quality films than the dummy gate dielectrics, because they are exposed to fewer processing steps than the dummy gate dielectrics. Further, the dummy gate dielectrics may be formed thinner than dummy gate dielectrics that are used as interfacial layers, allowing for a reduction in etching losses when removing the dummy gate dielectrics. After the replacement interfacial layers are formed, the thickness of the replacement interfacial layers in some regions (e.g., input/output regions) is increased by an anneal process. Increasing the thickness of these replacement interfacial layers can reduce the leakage current of the devices in the input/output regions. The performance of the devices may thus be improved. FIG. 1 illustrates an example of Fin Field-Effect Transistors (FinFETs), in accordance with some embodiments. FIG. 1 is a three-dimensional view, where some features of the FinFETs are omitted for illustration clarity. The FinFETs include fins 52 extending from a substrate 50 (e.g., a semicond