US-20260129970-A1 - SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

US20260129970A1US 20260129970 A1US20260129970 A1US 20260129970A1US-20260129970-A1

Abstract

A semiconductor structure includes a substrate having a first doping type, a first conductive structure disposed within the substrate and having a bottom portion and a sidewall portion disposed over and coupled to the bottom portion, a first isolation layer disposed under the first conductive structure and within the substrate, and a semiconductor device disposed over the first conductive structure and including an oxide layer disposed over a first surface of the substrate. The first conductive structure is partially enclosed by the oxide layer and the first isolation layer, at least a portion of the semiconductor device is surrounded by the sidewall portion of the first conductive structure, and the semiconductor device is separated from the first conductive structure.

Inventors

Hung-Te Lin

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Dates

Publication Date: 20260507
Application Date: 20241106

Claims (20)

1 . A semiconductor structure, comprising: a substrate having a first doping type; a first conductive structure disposed within the substrate and having a bottom portion and a sidewall portion disposed over and coupled to the bottom portion; a first isolation layer disposed under the first conductive structure and within the substrate; and a semiconductor device disposed over the first conductive structure and including an oxide layer disposed over a first surface of the substrate, wherein the first conductive structure is partially enclosed by the oxide layer and the first isolation layer, at least a portion of the semiconductor device is surrounded by the sidewall portion of the first conductive structure, and the semiconductor device is separated from the first conductive structure.
2 . The semiconductor structure of claim 1 , wherein the first conductive structure further includes an upper portion coupled to the sidewall portion, the sidewall portion is disposed between the bottom portion and the upper portion, and the upper portion is in contact with the oxide layer.
3 . The semiconductor structure of claim 2 , wherein the upper portion extends from the sidewall portion and away from the semiconductor device.
4 . The semiconductor structure of claim 1 , wherein an angle between the bottom portion and the sidewall portion is greater than 90°.
5 . The semiconductor structure of claim 1 , further comprising: a first semiconductor material layer disposed between the first conductive structure and the semiconductor device, wherein the semiconductor material layer has a second doping type opposite to the first doping type.
6 . The semiconductor structure of claim 1 , further comprising: a second conductive structure disposed within the substrate and adjacent to the first conductive structure; and a second semiconductor material layer disposed within the substrate and surrounded by the second conductive structure, wherein the second semiconductor material layer has the first doping type, and the second conductive structure is electrically isolated from the first conductive structure.
7 . The semiconductor structure of claim 6 , further comprising: a second isolation layer disposed under the second conductive structure, wherein the second isolation layer is disposed between the second conductive structure and the substrate.
8 . The semiconductor structure of claim 6 , wherein the second conductive structure is sandwiched between and in contact with the substrate and the second semiconductor material layer.
9 . The semiconductor structure of claim 1 , further comprising: a contact electrically connected to the first conductive structure, wherein the contact extends through the oxide layer.
10 . The semiconductor structure of claim 1 , further comprising: a first isolation structure disposed between the first conductive structure and the semiconductor device; and a second isolation structure coupled to the first conductive structure, wherein at least a portion of the first conductive structure is disposed between the first isolation structure and the second isolation structure in a plan view.
11 . A semiconductor structure, comprising: a substrate having a surface; a conductive structure disposed within the substrate and having a first bottom portion, a first sidewall portion disposed over and coupled to the first bottom portion, and a first upper portion coupled to the first sidewall portion and exposed through the surface; and a semiconductor device disposed over and electrically connected to the conductive structure, wherein the first sidewall portion is disposed between the first bottom portion and the upper portion, and at least a portion of the semiconductor device is surrounded by the first sidewall portion of the conductive structure in a plan view.
12 . The semiconductor structure of claim 11 , further comprising: a first isolation layer disposed under the conductive structure; and a first doped layer disposed over the conductive structure and between the conductive structure and the semiconductor device, wherein the conductive structure is disposed between the first isolation layer and the first doped layer.
13 . The semiconductor structure of claim 11 , wherein the conductive structure includes metal silicide.
14 . The semiconductor structure of claim 11 , wherein the conductive structure further includes a second bottom portion separated from the first bottom portion, a second sidewall portion disposed over and coupled to the second bottom portion, and a second upper portion coupled to the second sidewall portion and exposed through the surface.
15 . The semiconductor structure of claim 14 , further comprising: a first semiconductor material layer in contact with the first bottom portion, the first sidewall portion and the first upper portion; and a second semiconductor material layer having a first doping type and in contact with the second bottom portion, the second sidewall portion, the second upper portion and the first semiconductor material layer, wherein the first semiconductor material layer has a second doping type opposite to the first doping type.
16 . A method of manufacturing a semiconductor structure, comprising: providing a substrate having a surface; forming a recess on the surface of the substrate; forming a conductive structure within and conformal to the recess; forming a semiconductor material layer in the recess and over the conductive structure; doping the semiconductor material layer to form a doped semiconductor material layer; and forming a semiconductor device over the doped semiconductor material layer, wherein the semiconductor device is electrically connected to the conductive structure, wherein at least a portion of the semiconductor device is surrounded by the conductive structure.
17 . The method of claim 16 , further comprising: planarizing the semiconductor material layer, the conductive structure and the substrate before the formation of the semiconductor device, wherein a top surface of the semiconductor material layer and a top surface of the conductive structure are made coplanar with the surface of the substrate.
18 . The method of claim 16 , further comprising: forming a first isolation layer in the recess before the formation of the conductive structure; and forming a first doped layer in the recess and over the conductive structure before forming the semiconductor material layer, wherein the conductive structure is formed between the first isolation layer and the first doped layer.
19 . The method of claim 16 , wherein the formation of the conductive structure includes: forming a second doped layer in the recess; and annealing the substrate to drive the second doped layer to the conductive structure.
20 . The method of claim 16 , further comprising: forming a first isolation structure surrounded by the conductive structure; forming a second isolation structure coupled to the conductive structure; and electrically coupling a contact to the conductive structure, wherein the first isolation structure is disposed between the conductive structure and the semiconductor device, and the contact is disposed between the first isolation structure and the second isolation structure in a plan view.

Description

BACKGROUND The semiconductor industry has experienced rapid growth due to ongoing improvements in integration density of a variety of electrical components. To accommodate miniaturized scales of many semiconductor devices, various technologies and applications have been developed for wafer-level packaging, involving greater numbers of different components with different functions. As semiconductor technologies continually advance, embedding of electrical components into a semiconductive substrate has emerged as an effective approach to further reducing a physical size of a semiconductor device. The electrical component is at least partially embedded within the semiconductive substrate in order to minimize an amount of space occupied above the semiconductive substrate. Such embedding processes utilize sophisticated techniques, and improvements are desired. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a schematic top view of a semiconductor structure in accordance with some embodiments of the present disclosure. FIGS. 2 and 3 are schematic cross-sectional views taken along a line A-A' in FIG. 1. FIG. 4 is a cross-sectional view of a semiconductor structure in accordance with some embodiments of the present disclosure. FIGS. 5, 6 and 7 are cross-sectional views of a portion of a semiconductor structure in accordance with some embodiments of the present disclosure. FIG. 8 is a schematic top view of a semiconductor structure in accordance with some embodiments of the present disclosure. FIG. 9 is a schematic cross-sectional view taken along a line B-B' in FIG. 8. FIG. 10 is a flow diagram of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure. FIG. 11 is a flow diagram of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure. FIGS. 12 to 24 are cross-sectional views of one or more stages of a method of manufacturing a semiconductor structure in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features are not in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “upper,” “on” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, although the terms such as "first," "second" and "third" describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as "first," "second" and "third" when used herein do not imply a sequence or order unless clearly indicated by the context. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the normal variation found in the respective testing measurements. Also, as used herein, the terms "substantially," "approximately" and “about” gene