US-20260129971-A1 - MULTI-FINGER SEMICONDUCTOR DEVICES WITH DUMMY GATE STRUCTURES

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to multi-finger semiconductor devices with dummy gate structures and methods of manufacture. The structure includes: a plurality of active gate structures over a semiconductor substrate; a shared diffusion region in the semiconductor substrate between adjacent active gate structures of the plurality of gate structures; and a gate structure shorted to the shared diffusion region.

Inventors

• Kaustubh Shanbhag
• Vibhor Jain
• Judson Robert Holt
• Tamilmani Ethirajan
• Teng-Yin LIN

Assignees

• GLOBALFOUNDRIES U.S. INC.

Dates

Publication Date

20260507

Application Date

20241107

Claims (20)

1. 1 . A structure comprising: a plurality of active gate structures over a semiconductor substrate; a shared diffusion region in the semiconductor substrate between adjacent active gate structures of the plurality of gate structures; and a gate structure shorted to the shared diffusion region.
2. 2 . The structure of claim 1 , wherein the gate structure comprises a gate electrode contacting the shared diffusion region.
3. 3 . The structure of claim 2 , wherein the gate structure is devoid of a gate dielectric material between the gate electrode and the shared diffusion region.
4. 4 . The structure of claim 2 , further comprising a gate dielectric material between a portion of the gate electrode and the shared diffusion region.
5. 5 . The structure of claim 1 , wherein the shared diffusion region is a shared drain region.
6. 6 . The structure of claim 2 , further comprising a plurality of contacts connecting to the gate electrode of the gate structure and the shared diffusion region on opposing sides of the gate structure, and a wiring structure connecting to the plurality of contacts.
7. 7 . The structure of claim 2 , further comprising a contact which spans over the gate structure and connecting to the gate electrode of the gate structure and the shared diffusion region on opposing sides of the gate structure.
8. 8 . The structure of claim 2 , further comprising a plurality of contacts each of which partially span over the gate structure, a first contact connecting to the gate electrode of the gate structure on a first side and the shared diffusion region adjacent to the first side and a second contact connecting to the gate electrode of the gate structure on a second side of the shared diffusion region adjacent to the second side, and a wiring structure connecting to the plurality of contacts.
9. 9 . The structure of claim 8 , wherein the first contact and the second contact are located at different locations along a length of the gate structure.
10. 10 . The structure of claim 1 , further comprising a second gate structure shorted to and over the shared diffusion region.
11. 11 . The structure of claim 1 , further comprising contacts on opposing sides of the gate structure and connecting to the shared diffusion region.
12. 12 . The structure of claim 1 , wherein the shared diffusion region is shallow than an adjacent diffusion region.
13. 13 . A structure comprising: a plurality of active gate structures on a semiconductor substrate, the plurality of active gate structures each including a gate dielectric material and a gate electrode; a diffusion region shared amongst adjacent active gate structure of the plurality of gate structures; at least one gate structure comprising a gate electrode electrically connecting to the diffusion region; and contacts connecting to the diffusion region.
14. 14 . The structure of claim 13 , wherein the at least one gate structure comprises a gate dielectric material under a portion of the gate electrode.
15. 15 . The structure of claim 13 , further comprising a contact spanning over the gate structure and electrically connecting to the gate electrode and opposing sides of the diffusion region.
16. 16 . The structure of claim 13 , further comprising a plurality of contacts connecting to the gate electrode of the gate structure and opposing sides of the diffusion region, with a common wiring structuring connecting to the plurality of contacts.
17. 17 . The structure of claim 16 , wherein the plurality of contacts comprising a first contact spanning partially over and connecting to a first side of the gate electrode of the gate structure and a first side of the diffusion region and a second contact spanning partially over and connecting to a second side of the gate electrode of the gate structure and a second side of the diffusion region.
18. 18 . The structure of claim 13 , wherein the plurality of contacts comprising a first contact electrically connecting to a diffusion region on a first side of the gate structure and a second contact electrically connecting to the diffusion region on a second side of the gate structure.
19. 19 . The structure of claim 13 , wherein the plurality of active gate structures and the gate structure are parallel finger gate structures.
20. 20 . A method comprising: forming a plurality of active gate structures over a semiconductor substrate; forming a shared diffusion region in the semiconductor substrate between adjacent active gate structures of the plurality of gate structures; and forming a gate structure shorted to the shared diffusion region

Description

BACKGROUND The present disclosure relates to semiconductor structures and, more particularly, to multi-finger semiconductor devices with dummy gate structures and methods of manufacture. A multi-finger layout of a transistor consists of splitting a gate structure into multiple parallel fingers. A multi-finger gate MOSFET is used in RF CMOS analog circuit designs due to the increased circuit performance. An advantage of this is that parasitic capacitances and gate resistance can be simultaneously reduced. The multi-finger gate MOSFET can also exhibit area savings on the silicon substrate, as diffusion regions (e.g., source or drain regions) can be shared amongst adjacent gate structures. SUMMARY In an aspect of the disclosure, a structure comprises: a plurality of active gate structures over a semiconductor substrate; a shared diffusion region in the semiconductor substrate between adjacent active gate structures of the plurality of gate structures; and a gate structure shorted to the shared diffusion region. In an aspect of the disclosure, a structure comprises: a plurality of active gate structures on a semiconductor substrate, the plurality of active gate structures each including a gate dielectric material and a gate electrode; a diffusion region shared amongst adjacent active gate structure of the plurality of gate structures; at least one gate structure comprising a gate electrode electrically connecting to the diffusion region; and contacts connecting to the diffusion region. In an aspect of the disclosure, a method comprises: forming a plurality of active gate structures over a semiconductor substrate; forming a shared diffusion region in the semiconductor substrate between adjacent active gate structures of the plurality of gate structures; and forming a gate structure shorted to the shared diffusion region. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure is described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure. FIG. 1A shows a top view of a structure and respective fabrication processes in accordance with aspects of the present disclosure. FIG. 1B shows a cross-sectional view of the structure of FIG. 1A along lines “A”-“A”. FIG. 2 shows a structure in accordance with additional aspects of the present disclosure. FIG. 3 shows a structure in accordance with further aspects of the present disclosure. FIG. 4A shows a top view of a structure in accordance with further aspects of the present disclosure. FIG. 4B shows a cross-sectional view of the structure of FIG. 4A along lines “A”-“A”. FIG. 4C shows a cross-sectional view of the structure of FIG. 4A along lines “B”-“B”. FIG. 5A shows a top view of a structure in accordance with additional aspects of the present disclosure. FIG. 5B shows a cross-sectional view of the structure of FIG. 5A along lines “A”-“A”. FIG. 6 shows a structure with multiple dummy gate structures in a shared diffusion region in accordance with additional aspects of the present disclosure. FIGS. 7A-7D show fabrication steps for manufacturing the structure of FIGS. 1A and 1B. DETAILED DESCRIPTION The present disclosure relates to semiconductor structures and, more particularly, to multi-finger semiconductor devices with dummy gate structures and methods of manufacture. More specifically, the multi-finger semiconductor devices include dummy gate structures between active gate structures, with the dummy gate structures shorted to a shared drain region or source region of adjacent active gate structures. Advantageously, the multi-finger semiconductor devices with dummy gates structures will exhibit improved thermal performance (e.g., an increase in thermal resistance (R-values)), with increased contact density, a larger diffusion region and area savings. The structures of the present disclosure can be manufactured in a number of ways using a number of different tools. In general, though, the methodologies and tools are used to form structures with dimensions in the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to manufacture the structures of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the structures are built on wafers and are realized in films of material patterned by photolithographic processes on the top of a wafer. In particular, the fabrication of the structures uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) applying a patterned mask on top of the films by photolithographic imaging, and (iii) etching the films selectively to the mask. In addition, precleaning processes may be used to clean etched surfaces of any contaminants, as is known in the art. Moreover, when necessary, rapid thermal anneal processes may be used to drive-in dopants or material layers as is known in the art. FIG. 1A shows a top view of a stru