US-20260129973-A1 - HYBRID DRIVE ELECTRONIC DEVICE FOR ENHANCING DISPLAY PERFORMANCE OF LOW-GRAYSCALE PIXELS

Abstract

An electronic device includes an electronic unit, an integrated circuit, a first transistor and a second transistor. The integrated circuit is used to provide a sweep signal. The first transistor includes a first semiconductor, a first terminal electrically connected to a power source, a second terminal electrically connected to the electronic unit, and a first control terminal. The second transistor includes a second semiconductor, a third terminal configured to receive the sweep signal, a fourth terminal electrically connected to the first control terminal of the first transistor, and a second control terminal configured to receive a switch signal. The first transistor has a first channel width-to-length ratio, the second transistor has a second channel width-to-length ratio, of the first channel width-to-length ratio to the second channel width-to-length ratio is greater than or equal to 0.03 and less than or equal to 80.5.

Inventors

• Jia-Yuan CHEN
• Sheng-Feng Huang
• Tsung-Han Tsai
• Kuan-Feng LEE

Assignees

• Innolux Corporation

Dates

Publication Date

20260507

Application Date

20250924

Priority Date

20241104

Claims (20)

1. 1 . An electronic device comprising: an electronic unit; an integrated circuit configured to provide a sweep signal; a first transistor comprising a first semiconductor, a first terminal, a second terminal and a first control terminal, wherein the first terminal is electrically connected to a power source, and the second terminal is electrically connected to the electronic unit; and a second transistor comprising a second semiconductor, a third terminal, a fourth terminal and a second control terminal, wherein the third terminal is configured to receive the sweep signal, the fourth terminal is electrically connected to the first control terminal of the first transistor, and the second control terminal is configured to receive a switch signal; wherein the first transistor has a first channel width-to-length ratio, the second transistor has a channel width-to-length ratio, and a ratio of the first channel width-to-length ratio to the second channel width-to-length ratio is greater than or equal to 0.03 and less than or equal to 80.5.
2. 2 . The electronic device of claim 1 , wherein at least one of the first semiconductor and the second semiconductor is an oxide semiconductor.
3. 3 . The electronic device of claim 2 , wherein the ratio of the first channel width-to-length ratio to the second channel width-to-length ratio is greater than or equal to 0.05 and less than or equal to 57.5.
4. 4 . The electronic device of claim 2 , wherein both the first semiconductor and the second semiconductor are oxide semiconductors.
5. 5 . The electronic device of claim 4 , wherein the ratio of the first channel width-to-length ratio to the second channel width-to-length ratio is greater than or equal to 0.2 and less than or equal to 17.3.
6. 6 . The electronic device of claim 1 , wherein the first transistor has a first channel length, the second transistor has a second channel length, and the first channel length is greater than the second channel length.
7. 7 . The electronic device of claim 6 , wherein a ratio of the first channel length to the second channel length is greater than or equal to 1.05 and less than or equal to 3.5.
8. 8 . The electronic device of claim 7 , wherein the ratio of the first channel length to the second channel length is greater than or equal to 1.1 and less than or equal to 2.2.
9. 9 . The electronic device of claim 1 , further comprising a metal oxide element overlapping the first semiconductor, wherein the first semiconductor is an oxide semiconductor and disposed between the first control terminal and the metal oxide element.
10. 10 . The electronic device of claim 9 , wherein in a top view of the electronic device, the metal oxide element is greater than the first semiconductor in width.
11. 11 . The electronic device of claim 9 , further comprising a light shielding element overlapping the first semiconductor, wherein the metal oxide element is disposed between the first semiconductor and the light shielding element.
12. 12 . The electronic device of claim 11 , wherein the light shielding element directly contacts the metal oxide element.
13. 13 . The electronic device of claim 11 , wherein the light shielding element is greater than the metal oxide element in width.
14. 14 . The electronic device of claim 9 , wherein the first semiconductor comprises two openings, and the first control terminal is disposed between the two openings in a top view of the electronic device.
15. 15 . The electronic device of claim 1 , further comprising: a first metal oxide element overlapping the first semiconductor; and a second metal oxide element overlapping the second semiconductor; wherein the first metal oxide element has a first area, the second metal oxide element has a second area, and a ratio of the first area to the second area is greater than or equal to 1.1 and less than or equal to 10.2.
16. 16 . The electronic device of claim 1 , wherein the first control terminal and the first semiconductor overlap in a first region, the second control terminal and the second semiconductor overlap in a second region, the first region has a third area, the second region has a fourth area, and a ratio of the third area to the fourth area is greater than or equal to 1.2 and less than or equal to 7.6.
17. 17 . The electronic device of claim 1 , further comprising a third transistor having a third control terminal electrically connected to the first control terminal, wherein the first transistor is different from the third transistor in channel length.
18. 18 . The electronic device of claim 1 , wherein the electronic unit is a diode.
19. 19 . The electronic device of claim 1 , wherein the electronic device has a first portion and a second portion, the first portion surrounds the second portion, and the first transistor and the integrated circuit are both in the second portion.
20. 20 . The electronic device of claim 1 , wherein the electronic device has a first portion and a second portion, the first portion surrounds the second portion, the first transistor is in the second portion and the integrated circuit is in the first portion.

Description

BACKGROUND OF THE DISCLOSURE 1. Field of the Disclosure The disclosure is related to an electronic device, and more particularly to a hybrid drive electronic device. 2. Description of the Prior Art In the prior art, multiple transistors were used to hybridly drive electronic devices, enabling the adjustment of various parameters and achieving diverse functionalities. For example, certain transistors were used to regulate voltage oscillation, while others controlled current frequency. However, if each group of pixels requires a pulse width modulation (PWM) transistor circuit and a pulse amplitude modulation (PAM) transistor circuit, the resulting large number of transistors can occupy significant space, limiting improvements in resolution. Therefore, reducing the number of transistors to save space has become a critical challenge. SUMMARY OF THE DISCLOSURE An embodiment discloses an electronic device comprising an electronic unit, an integrated circuit, a first transistor and a second transistor. The integrated circuit is configured to provide a sweep signal. The first transistor includes a first semiconductor, a first terminal, a second terminal and a first control terminal. The first terminal is electrically connected to a power source, and the second terminal is electrically connected to the electronic unit. The second transistor includes a second semiconductor, a third terminal, a fourth terminal and a second control terminal. The third terminal is configured to receive the sweep signal, the fourth terminal is electrically connected to the first control terminal of the first transistor, and the second control terminal is configured to receive a switch signal. The first transistor has a first channel width-to-length ratio, the second transistor has a second channel width-to-length ratio, and a ratio of the first channel width-to-length ratio to the second channel width-to-length ratio is greater than or equal to 0.03 and less than or equal to 80.5. These and other objectives of the present disclosure will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the embodiment that is illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a circuit of an electronic device according to an embodiment of the disclosure. FIG. 2A is a schematic diagram of an electronic device according to another embodiment of the disclosure. FIG. 2B is a schematic diagram of an electronic device according to another embodiment of the disclosure. FIG. 2C is a schematic diagram of a circuit of an electronic device according to another embodiment of the disclosure. FIG. 3A is a cross-sectional view of the electronic device of FIG. 1. FIG. 3B is a top view of a transistor in FIG. 3A. FIG. 3C is a schematic diagram of the driving transistor in FIG. 3A. FIG. 4 is a top view of a transistor according to another embodiment of the disclosure. FIG. 5A is a top view of a driving transistor according to another embodiment of the disclosure. FIG. 5B is a schematic diagram of the current curve of the driving transistor in FIG. 5A. FIG. 6 is a cross-sectional view of an electronic device according to another embodiment of the disclosure. FIG. 7A is a schematic diagram of a circuit of an electronic device according to another embodiment of the disclosure. FIG. 7B is a cross-sectional view of an embodiment of the electronic device according to FIG. 7A. FIG. 7C is a cross-sectional view of another embodiment of the electronic device according to FIG. 7A. FIG. 8A is a schematic diagram of a circuit of an electronic device according to another embodiment of the disclosure. FIG. 8B is a schematic diagram of an electronic device according to another embodiment of the disclosure. FIG. 9 is a cross-sectional view of the electronic device of FIG. 8B. FIG. 10 is a schematic diagram of an electronic device according to another embodiment of the disclosure. FIG. 11 is a waveform diagram of a circuit of an electronic device according to an embodiment of the disclosure. FIG. 12 is a schematic diagram of a circuit of an electronic device according to another embodiment of the disclosure. DETAILED DESCRIPTION The structure, number of components, number of layers, positional arrangement, proportions, and other attributes of the icons described herein are provided solely as illustrative examples to facilitate understanding of the embodiments and should not be construed as limiting the style or scope of the embodiments. Furthermore, any ordinal terms such as ‘first,’ ‘second,’ etc., are used solely for distinguishing between different components and do not imply any specific sequence, order, or significance in the manufacturing process. Certain terms are used throughout the description and claims of the present disclosure to refer to specific components. It should be understood by those skilled in the art that different manufacturers of electron