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US-20260129977-A1 - CONTROLLABLE TRIGGERED ELECTROSTATIC DISCHARGE DEVICE WITH NANOSHEET GATES

US20260129977A1US 20260129977 A1US20260129977 A1US 20260129977A1US-20260129977-A1

Abstract

A semiconductor device includes a base including a first doped region, a second doped region and a plurality of nanosheet gates, a collector including a third doped region, and an emitter including a fourth doped region. The plurality of nanosheet gates is configured to control a resistance of the base.

Inventors

  • Anindya Nath
  • Robert Gauthier
  • Masoud Zabihi
  • Anthony I-Chih Chou
  • Ruilong Xie

Assignees

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date
20260507
Application Date
20241101

Claims (20)

  1. 1 . A semiconductor device, comprising: a base comprising a first doped region, a second doped region and a plurality of nanosheet gates; a collector comprising a third doped region; and an emitter comprising a fourth doped region, wherein the plurality of nanosheet gates is configured to control a resistance of the base.
  2. 2 . The semiconductor device of claim 1 , wherein the semiconductor device is a lateral N-type/P-type/N-type (LNPN) device, or a lateral P-type/N-type/P-type (LPNP) device.
  3. 3 . The semiconductor device of claim 1 , further comprising: a first well region below the collector and the emitter; and a second well region below the first well region and the base.
  4. 4 . The semiconductor device of claim 1 , wherein each of the base, the emitter, and the collector further comprises: a spacer layer over sidewalls of a set of gate regions.
  5. 5 . The semiconductor device of claim 1 , wherein each of the base, the emitter, and the collector further comprises: a frontside contact.
  6. 6 . The semiconductor device of claim 1 , wherein: the plurality of nanosheet gates comprises alternative layers extended horizontally between a corresponding doped region and a gate region.
  7. 7 . The semiconductor device of claim 6 , wherein the alternative layers include silicon.
  8. 8 . A method of fabricating a semiconductor device, the method comprising: forming a base comprising a first doped region, a second doped region and a plurality of nanosheet gates; forming a collector comprising a third doped region; forming an emitter comprising a fourth doped region; and controlling a resistance of the base via the plurality of nanosheet gates.
  9. 9 . The method of claim 8 , wherein the semiconductor device is a lateral N-type/P-type/N-type (LNPN) device, or a lateral P-type/N-type/P-type (LPNP) device.
  10. 10 . The method of claim 8 , further comprising: forming a first well region below the collector and the emitter; and forming a second well region below the first well region and the base.
  11. 11 . The method of claim 8 , wherein forming each of the base, the emitter, and the collector further comprises: forming a spacer layer over sidewalls of a gate region.
  12. 12 . The method of claim 8 , wherein forming the plurality of nanosheet gates comprises: extending the plurality of nanosheet gates horizontally between a corresponding doped region and a gate region.
  13. 13 . The method of claim 8 , wherein the plurality of nanosheet gates includes silicon.
  14. 14 . A semiconductor device, comprising: a base comprising a first doped region, a second doped region, a plurality of nanosheet gates; a collector comprising a third doped region; and an emitter comprising a fourth doped region, wherein the plurality of nanosheet gates and an electrical connection between he base and the emitter are configured to control a resistance of the base.
  15. 15 . The semiconductor device of claim 14 , wherein the semiconductor device is a lateral N-type/P-type/N-type (LNPN) device, or a lateral P-type/N-type/P-type (LPNP) device.
  16. 16 . The semiconductor device of claim 14 , further comprising: a first well region below the collector and the emitter; and a second well region below the first well region and the base.
  17. 17 . The semiconductor device of claim 14 , wherein each of the base, the emitter, and the collector further comprises: a spacer layer over sidewalls of a set of gate regions.
  18. 18 . The semiconductor device of claim 14 , wherein each of the base, the emitter, and the collector further comprises: the plurality of nanosheet gates comprises alternative layers extended horizontally between a corresponding doped region and a gate region.
  19. 19 . The semiconductor device of claim 18 , wherein the alternative layers include silicon.
  20. 20 . The semiconductor device of claim 14 , wherein each of the base, the emitter, and the collector further comprises: a frontside contact.

Description

BACKGROUND Technical Field The present disclosure generally relates to semiconductors, and more particularly, to controllable triggered nanosheet gate electrostatic discharge structure, and methods of creation thereof. Description of Related Art The continuous miniaturization of transistors and their increasing density on chips are hallmark innovations in the semiconductor industry, closely following Moore's Law. This trend has enabled transistors to shrink to nanometer scales, allowing millions, and even billions, to be integrated onto a single chip. This advancement significantly boosts computational power and energy efficiency. The evolution towards system-on-chip architectures further enhances these capabilities by integrating various functionalities, such as processing and sensing, into a single chip. SUMMARY According to an embodiment, a semiconductor device includes a base having a base including a first doped region, a second doped region and a plurality of nanosheet gates, a collector including a third doped region, and an emitter including a fourth doped region. The plurality of nanosheet gates is configured to control a resistance of the base. In an embodiment, the semiconductor device is a lateral N-type/P-type/N-type (LNPN) device, or a lateral P-type/N-type/P-type (LPNP) device. In an embodiment, the semiconductor device includes a first well region below the collector and the emitter, and a second well region below the first well region and the base. In an embodiment, each of the base, the emitter, and the collector further includes a spacer layer over sidewalls of a set of gate regions. In an embodiment, each of the base, the emitter, and the collector includes a frontside contact. In an embodiment, the plurality of nanosheet gates includes alternative layers extended horizontally between the corresponding doped region and a gate region. In an embodiment, the alternative layers include silicon. According to an embodiment, a method of fabricating a semiconductor device includes forming a base including a first doped region, a second doped region and a plurality of nanosheet gates, forming a collector including a third doped region, forming an emitter including a fourth doped region, and controlling a resistance of the base via the nanosheet gates. In an embodiment, the semiconductor device is a lateral N-type/P-type/N-type (LNPN) device, or a lateral P-type/N-type/P-type (LPNP) device. In an embodiment, the method includes forming a first well region below the collector and the emitter, and forming a second well region below the first well region and the base. In an embodiment, forming each of the base, the emitter, and the collector includes forming a spacer layer over sidewalls of a gate region. In an embodiment, forming the plurality of nanosheet gates includes extending the plurality of nanosheet gates horizontally between a corresponding doped region and a gate region. In an embodiment, the plurality of nanosheet gates includes silicon. According to an embodiment, a semiconductor deice includes a base including a first doped region, a second doped region, a plurality of nanosheet gates, a collector including a third doped region, and an emitter including a fourth doped region. The plurality of nanosheet gates and an electrical connection between the base and the emitter are configured to control a resistance of the base. In an embodiment, the semiconductor device is a lateral N-type/P-type/N-type (LNPN) device, or a lateral P-type/N-type/P-type (LPNP) device. In an embodiment, the semiconductor device includes a first well region below the collector and the emitter, and a second well region below the first well region and the base. In an embodiment, each of the base, the emitter, and the collector includes a spacer layer over sidewalls of a set of gate regions. In an embodiment, each of the base, the emitter, and the collector includes the plurality of nanosheet gates includes alternative layers extended horizontally between the corresponding doped region and a gate region. In an embodiment, the alternative layers include silicon. In an embodiment, each of the base, the emitter, and the collector includes a frontside contact. These and other features will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The drawings are of illustrative embodiments. They do not illustrate all embodiments. Other embodiments may be used in addition or instead. Details that may be apparent or unnecessary may be omitted to save space or for more effective illustration. Some embodiments may be practiced with additional components or steps and/or without all the components or steps that are illustrated. When the same numeral appears in different drawings, it refers to the same or like components or steps. FIG. 1A illustrates exemplary circuitry of a planar complementary