US-20260129978-A1 - PROTECTION ELECTRONIC DEVICE FOR THE PREVENTION OF DAMAGES INDUCED BY PLASMA-ASSISTED PROCESSES, AND MANUFACTURING METHOD THEREOF

US20260129978A1US 20260129978 A1US20260129978 A1US 20260129978A1US-20260129978-A1

Abstract

An electronic device includes a circuit module and a protection module. The circuit module includes a P-N junction between a reference terminal and an electrical node, and metal connection lines coupled to the electrical node and configured to be charged due to antenna effect. The protection module includes an HV transistor and a capacitor. The capacitor is connected between the electrical node and the HV transistor and configured to turn on the HV transistor when the electrical node charges positively due to the antenna effect. The circuit module is thus maintained at a potential that does not damage the electronic device.

Inventors

Fausto CARACE
Simone MILITELLO

Assignees

STMICROELECTRONICS INTERNATIONAL N.V.

Dates

Publication Date: 20260507
Application Date: 20250915
Priority Date: 20240920

Claims (18)

1 . An electronic device, comprising: a circuit module comprising: a P-N junction electrically coupled between a reference terminal and an electrical node; and a plurality of metal connection lines electrically coupled to the electrical node and configured to be charged by positive electrical charges due to antenna effect when subject to a plasma treatment; and a protection module comprising: a first transistor having an N-channel, having a first and a second conduction terminal and a control terminal; and a capacitive circuit; wherein the second conduction terminal of the first transistor is electrically coupled to the electrical node, the first conduction terminal of the first transistor is electrically coupled to the reference terminal, and the control terminal of the first transistor is capacitively coupled to the electrical node through said capacitive circuit.
2 . The electronic device according to claim 1 , wherein said capacitive circuit includes a first capacitor comprising a first conductive plate, a second conductive plate and a third conductive plate; wherein the first conductive plate extends between the surface of a substrate and the lower connection line, the second conductive plate extends coplanar to the lower connection line, and the third conductive plate extends above the lower connection line and directly faces the second conductive plate through a respective portion of the dielectric layer; wherein the first conductive plate and the third conductive plate are electrically connected to the electrical node, and the second conductive plate is electrically connected to the control terminal of the first transistor.
3 . The electronic device according to claim 1 , wherein said capacitive circuit includes a first capacitor of the Metal-Oxide-Metal (MOM) type having a structure with interdigitated electrodes coplanar to the lower connection line and electrically connected respectively to the electrical node and to the control terminal of the first transistor.
4 . The electronic device according to claim 1 , wherein said capacitive circuit includes a first capacitor, the first capacitor comprising a first conductive plate and a second conductive plate; wherein the first conductive plate extends between a surface of a substrate and the lower connection line, and the second conductive plate extending above the lower connection line and directly facing the first conductive plate through a respective portion of the dielectric layer having a thickness greater than 100 nm, wherein the first conductive plate is electrically connected to the electrical node and the second conductive plate is electrically connected to the control terminal of the first transistor.
5 . The electronic device according to claim 1 , wherein said capacitive circuit includes a parallel connection between a capacitor and an intrinsic capacitance of the first transistor, said intrinsic capacitance being between the control terminal and the second conduction terminal.
6 . The electronic device according to claim 1 , wherein the first transistor has a body terminal electrically connected to the first conduction terminal and to the reference terminal.
7 . The electronic device according to claim 1 , wherein the control terminal of the first transistor is electrically coupled to the first conduction terminal of the first transistor.
8 . The electronic device according to claim 7 , wherein the control terminal of the first transistor is directly electrically connected to the first conduction terminal of the first transistor.
9 . The electronic device according to claim 7 , wherein the control terminal of the first transistor is electrically coupled to the first conduction terminal of the first transistor by a second capacitor.
10 . The electronic device according to claim 1 , wherein the first transistor has a threshold voltage comprised between 0.5 and 3V, and the capacitive circuit has a specific capacitance with a value comprised between 0.01 fF/μm 2 and 4.0 fF/μm 2 .
11 . The electronic device according to claim 1 , further comprising: a solid body having a surface and a dielectric layer extending on the surface of the solid body; wherein said metal connection lines are formed in said dielectric layer and comprise: a lower connection line, an upper connection line above the lower connection line, and at least one intermediate connection line between the lower connection line and the upper connection line; wherein the lower connection line is, among said metal connection lines, closest to the surface of the solid body, and the upper connection line is, among said metal connection lines, farthest from the surface of the solid body; wherein the control terminal of the first transistor is electrically coupled to the first conduction terminal of the first transistor by an electrical connection extending at least in part coplanar to the upper connection line or extending at least in part above the upper connection line.
12 . The electronic device according to claim 11 , wherein the solid body is of semiconductor material having P-type electrical conductivity and forms said reference terminal, the electronic device further comprising: a first doped region in the solid body, facing the surface, of the N type and having a first doping value; and a second doped region buried in the solid body, of the N-type and having a second doping value greater than the first doping value, wherein the second doped region extends between part of the first doped region and the solid body, in direct electrical contact with the first doped region and with the solid body; said P-N junction being formed at the interface between the first and the second doped regions and the solid body.
13 . The electronic device according to claim 12 , wherein said first doped region accommodates at least one second transistor, said metal connection lines being coupled to conduction terminals of said second transistor.
14 . A method of manufacturing an electronic device, comprising the steps of: forming a circuit module by: forming a P-N junction electrically coupled between a reference terminal and an electrical node; and forming, by one or more plasma-assisted processes, a plurality of metal connection lines electrically coupled to the electrical node and configured to be charged by positive electrical charges due to antenna effect when subject to said one or more plasma-assisted processes; and forming a protection module by: forming a first transistor having an N-channel, having a first and a second conduction terminal and a control terminal; and forming a capacitive circuit; wherein the second conduction terminal of the first transistor is electrically coupled to the electrical node, the first conduction terminal of the first transistor is electrically coupled to the reference terminal, and said capacitive circuit is formed between the control terminal of the first transistor and the electrical node to electrically couple the control terminal to the electrical node.
15 . The method according to claim 14 , further comprising the step of electrically coupling the control terminal of the first transistor to the first conduction terminal of the first transistor.
16 . The method according to claim 15 : wherein the step of forming the plurality of metal connection lines ends with forming an upper metal line; and wherein the step of electrically coupling the control terminal of the first transistor to the first conduction terminal comprises forming an electrical connection concurrently with the formation of the upper metal line.
17 . The method according to claim 14 , further comprising directly connecting the control terminal to the first conduction terminal of the first transistor.
18 . The method according to claim 14 , further comprising electrically coupling the control terminal to the first conduction terminal of the first transistor by a second capacitor.

Description

PRIORITY CLAIM This application claims the priority benefit of Italian Application for Patent No. 102024000021052 filed on Sep. 20, 2024, the content of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law. TECHNICAL FIELD The present invention relates to an electronic device and to a manufacturing method thereof, in particular a protection device, for the prevention of plasma-induced damages due to the charging by antenna effect of metal layers that inject positive charges into underlying doped regions, during the manufacturing processes. BACKGROUND In the technologies used for the manufacturing of a Very Large Scale Integration (VLSI) Integrated Circuit (IC), the formation of metal lines on a semiconductor substrate, in particular for the formation of metal interconnects, requires numerous plasma-assisted process steps. Such process steps include, for example: plasma-assisted deposition steps such as physical vapor depositions (e.g., of “sputtering” type), chemical vapor depositions (e.g., of Plasma Enhanced Chemical Vapor Deposition (PECVD) type) and plasma-assisted etching steps such as reactive ion etchings (e.g., Reactive Ion Etching (RIE)). These plasma-assisted process steps cause the injection of significant amounts of charge into doped regions within the semiconductor substrate and connected to metal areas having large dimensions, such as metal interconnection lines for example. The metal areas act in fact as charge collectors during these process steps and transfer the collected charges to the aforementioned doped regions. This effect is known as the “antenna effect”. Integrated circuits for smart power management (e.g., “Smart Power” integrated circuits) are known in the art. In Smart Power, but also Digital and Imaging integrated circuits, buried regions doped with N-type conductivity (called “Deep N-WELL” or “DNW”), extended in depth into the substrate, are used to insulate analog and/or digital circuit blocks from the substrate to protect them from noise and possible parasitic currents injected into the substrate by power stages. A disadvantage resulting from the use of DNWs is a less efficient discharge, towards a ground terminal through the substrate, of the charges accumulated during the plasma processes. This may lead the circuit blocks insulated by the DNWs to voltages high enough to be damaging, in particular damaging to gate oxides. For example, if a MOS transistor has a body terminal connected or coupled to a ground terminal and a gate terminal connected or coupled to a circuit block insulated by a DNW that charges during the plasma process, the potential difference between the body terminal and the gate terminal of the MOS transistor may lead to the breakdown of the gate oxide of the MOS transistor. A similar breakdown mechanism of the gate oxide of the MOS transistor may occur in case the body terminal is connected or belongs to a circuit block insulated by a DNW that charges during a plasma process, and the gate terminal is connected or coupled to a ground terminal. FIG. 1 schematically illustrates a part of an integrated circuit 1, in a triaxial system of axes x, y, z orthogonal to each other, in a lateral sectional view on the xz plane. The integrated circuit 1 comprises a solid body 2, which in turn includes: a substrate 4 of semiconductor material such as for example silicon (Si), or silicon carbide (SiC), or gallium nitride (GaN); a patterned oxide layer 5 that extends at a first face 4a of the substrate 4, and that includes openings through which portions of the first face 4a of the substrate 4 are exposed; and a dielectric layer 3 that extends on the patterned oxide layer 5, in direct contact with the patterned oxide layer 5 and with the exposed portions of the first face 4a of the substrate 4. The substrate 4 has, for example, a P-type electrical conductivity. In general, the substrate 4 may comprise one or more structural layers of semiconductor material, for example of the same material indicated above for the substrate 4; such one or more structural layers are, for example, grown epitaxially. The integrated circuit 1 further comprises a first circuit block 6 that extends at least in part into the substrate 4 and at least in part into the dielectric layer 3, and a second circuit block 8 that extends at least in part into the substrate 4 and at least in part into the dielectric layer 3, laterally and at a distance from the first circuit block 6 along the x axis. The first circuit block 6 includes a first P-type MOS transistor (“P-MOS”) 10 in a first N-type doped region (“first N-WELL”) 12 of the substrate 4 and an N-type MOS transistor (“N-MOS”) 14 in a P-type doped region (“P-WELL”) 16. The P-WELL region 16 is completely surrounded, in view on the XY plane, by the first N-WELL 12 and faces the first face 4a of the substrate 4. The first circuit block 6 also includes a first N-type doped buried region (“first Deep N-WELL” or “fir