US-20260129985-A1 - IMAGE SENSOR PIXEL CELL WITH MULTI-GATE TRANSFER TRANSISTOR

Abstract

A pixel cell for an image sensor includes a first photodiode, a second photodiode, and a floating diffusion, each disposed within a semiconductor material. The pixel cell further includes a multi-gate transfer transistor configured to selectively couple the first photodiode and the second photodiode to the floating diffusion to transfer image charge from the first photodiode or the second photodiode to the floating diffusion. The multi-gate transfer transistor includes a plurality of separated gate electrodes including a first gate electrode disposed proximate to the first photodiode, a second gate electrode disposed proximate to the second photodiode, and a shared gate electrode disposed proximate to the floating diffusion. The multi-gate transfer transistor further includes an isolation structure disposed within the semiconductor substrate between the first photodiode and the second photodiode.

Inventors

• Duli Mao
• Yuanliang Liu
• Bill Phan
• Woon Il Choi
• Po-Chun Chiu
• Tomas Geurts

Assignees

• OMNIVISION TECHNOLOGIES, INC.

Dates

Publication Date

20260507

Application Date

20241107

Claims (20)

1. 1 . A pixel cell for an image sensor, comprising: a first photodiode, a second photodiode, and a floating diffusion, each disposed within a semiconductor material; and a multi-gate transfer transistor configured to selectively couple the first photodiode and the second photodiode to the floating diffusion to transfer image charge from the first photodiode or the second photodiode to the floating diffusion, wherein the multi-gate transfer transistor includes: a plurality of separated gate electrodes including a first gate electrode disposed proximate to the first photodiode, a second gate electrode disposed proximate to the second photodiode, and a shared gate electrode disposed proximate to the floating diffusion; and an isolation structure disposed within the semiconductor material between the first photodiode and the second photodiode.
2. 2 . The pixel cell of claim 1 , wherein the isolation structure is further disposed between the first gate electrode and the second gate electrode when the pixel cell is viewed from a plan view.
3. 3 . The pixel cell of claim 2 , wherein the multi-gate transfer transistor further comprises a gate dielectric disposed between the semiconductor material and each of the first gate electrode, the second gate electrode, and the shared gate electrode, wherein the isolation structure includes a trench isolation structure and an isolation implant region aligned with the trench isolation structure, wherein the isolation implant region is oppositely doped relative to the first photodiode and the second photodiode, and wherein the isolation implant region is disposed between the trench isolation structure and the gate dielectric.
4. 4 . The pixel cell of claim 1 , wherein the multi-gate transfer transistor further comprises: a gate dielectric disposed between the semiconductor material and each of the first gate electrode, the second gate electrode, and the shared gate electrode; and a doped channel region disposed within the semiconductor material proximate to the shared gate electrode, wherein the doped channel region extends from the floating diffusion towards the first photodiode or the second photodiode, wherein the doped channel region is separate from the first photodiode and the second photodiode, and wherein the doped channel region has a same conductivity type relative to the floating diffusion.
5. 5 . The pixel cell of claim 1 , wherein the first gate electrode, the second gate electrode, and the shared gate electrode extend along a common lateral plane parallel to a first side of the semiconductor material.
6. 6 . The pixel cell of claim 1 , wherein the shared gate electrode is disposed between the floating diffusion and the first gate electrode when the pixel cell is viewed from a plan view, wherein the shared gate electrode is further disposed between the floating diffusion and the second gate electrode when the pixel cell is viewed from the plan view.
7. 7 . The pixel cell of claim 1 , further comprising: a third photodiode and a fourth photodiode, each disposed within the semiconductor material; and a second multi-gate transfer transistor configured to selectively couple the third photodiode and the fourth photodiode to the floating diffusion to transfer image charge from the third photodiode or the fourth photodiode to the floating diffusion, wherein the second multi-gate transfer transistor includes: a plurality of second separated gate electrodes, including a third gate electrode disposed proximate to the third photodiode, a fourth gate electrode disposed proximate to the fourth gate electrode, and a second shared gate electrode disposed proximate to the floating diffusion.
8. 8 . The pixel cell of claim 7 , wherein the floating diffusion is disposed between the shared gate electrode and the second shared gate electrode when the pixel cell is viewed from a plan view, wherein the shared gate electrode and the second shared gate electrode are each disposed between the first gate electrode and the third gate electrode, and wherein the shared gate electrode and the second shared gate electrode are each further disposed between the second gate electrode and the fourth gate electrode.
9. 9 . The pixel cell of claim 1 , wherein a first longitudinal edge of the first gate electrode is parallel to a second longitudinal edge of the second gate electrode, and wherein a third longitudinal edge of the shared gate electrode is perpendicular to the first longitudinal edge of the first gate electrode and the second longitudinal edge of the second gate electrode, wherein a fourth longitudinal edge of the shared transfer gate is parallel to the third longitudinal edge, and wherein the fourth longitudinal edge is smaller than the third longitudinal edge.
10. 10 . The pixel cell of claim 1 , wherein the first gate electrode and the second gate electrode at least partially enclose the shared gate electrode such that the shared gate electrode is respectively separated from the first photodiode and the second photodiode by the first gate electrode and the second gate electrode.
11. 11 . The pixel cell of claim 1 , further comprising circuitry formed within a transistor region, wherein the floating diffusion is disposed between the shared gate electrode and the circuitry.
12. 12 . An image sensor, comprising: a pixel cell included in a plurality of pixel cells arranged in rows and columns to form a pixel cell array, wherein the pixel cell includes: a first photodiode, a second photodiode, and a floating diffusion, each disposed within a semiconductor material; and a multi-gate transfer transistor configured to selectively couple the first photodiode and the second photodiode to the floating diffusion to transfer image charge from the first photodiode or the second photodiode to the floating diffusion, wherein the multi-gate transfer transistor includes: a plurality of separated gate electrodes including a first gate electrode disposed proximate to the first photodiode, a second gate electrode disposed proximate to the second photodiode, and a shared gate electrode disposed proximate to the floating diffusion; and a control circuit configured to control operation of the image sensor.
13. 13 . The image sensor of claim 12 , wherein the control circuit is further configured to initiate a first charge transfer period for the first photodiode by simultaneously applying a first voltage to the first gate electrode and a second voltage to the shared gate electrode.
14. 14 . The image sensor of claim 13 , wherein the first voltage and the second voltage are each positive, and wherein the second voltage applied to the shared gate electrode is greater than the first voltage applied to the first gate electrode during the first charge transfer period to form a potential gradient to facilitate image charge transfer from the first photodiode to the floating diffusion.
15. 15 . The image sensor of claim 13 , wherein the control circuit is further configured to terminate the first charge transfer period for the first photodiode by transitioning the first voltage applied to the first gate electrode to a third voltage and further transitioning the second voltage applied to the shared gate electrode to a fourth voltage.
16. 16 . The image sensor of claim 15 , wherein the third voltage is negative and the fourth voltage is negative or zero, and wherein the fourth voltage is greater than the third voltage.
17. 17 . The image sensor of claim 15 , wherein the control circuit is further configured such that the transitioning the second voltage applied to the shared gate electrode to the fourth voltage occurs after the transitioning the first voltage applied to the first gate electrode to the third voltage.
18. 18 . The image sensor of claim 12 , wherein during a high conversion gain readout operation for the pixel cell, voltage levels applied to the first gate electrode, the second gate electrode, and the shared gate electrode configured by the control circuit correspond to low level voltages.
19. 19 . The image sensor of claim 12 , wherein during a low conversion gain readout operation for the pixel cell, voltage levels applied to the first gate electrode and the second gate electrode configured by the control circuitry correspond to low level voltages while a voltage level applied to the shared gate electrode corresponds to a high level voltage, and wherein the high level voltage is greater than the low level voltages.
20. 20 . The image sensor of claim 12 , wherein the shared gate electrode of the multi-gate transfer transistor is configured to be biased at different voltage level to modulate a conversion gain of the pixel cell during readout, wherein separation between the shared gate electrode and both the first gate electrode and the second gate electrode provides isolation between the floating diffusion and both the first photodiode and the second photodiode.

Description

TECHNICAL FIELD This disclosure relates generally to image sensors, and in particular but not exclusively, relates to CMOS image sensors and applications thereof. BACKGROUND INFORMATION Image sensors are one type of semiconductor device that have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, as well as, medical, automobile, and other applications. As image sensors are integrated into a broader range of electronic devices it is desirable to enhance their functionality, performance metrics, and the like in as many ways as possible (e.g., resolution, power consumption, dynamic range, size, etc.) through both device architecture design as well as image acquisition processing. However, it is appreciated that many of these metrics are inversely related. For example, pixel size may be increased to improve dynamic range but have increased noise. In another example, resolution may be increased by increasing the number of pixels, but if pixel size is maintained then the physical size of the image sensor increases. Accordingly, improving one or more performance metrics of semiconductor devices such as image sensors while mitigating adverse effects on other performance metrics remains challenging. The typical image sensor operates in response to image light reflected from an external scene being incident upon the image sensor. The image sensor includes an array of pixels having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charge upon absorption of the image light. The image charge photogenerated by the pixels may be measured as analog output image signals on column bit lines that vary as a function of the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is readout as analog image signals from the column bit lines and converted to digital values to produce digital images (i.e., image data) representative of the external scene. BRIEF DESCRIPTION OF THE DRAWINGS Non-limiting and non-exhaustive embodiments of the invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified. Not all instances of an element are necessarily labeled so as not to clutter the drawings where appropriate. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles being described. FIG. 1A illustrates a plan view of a pixel cell included in an image sensor with a multi-gate transfer transistor, in accordance with an embodiment of the disclosure. FIG. 1B illustrates a cross-sectional view along line W-W′ of the pixel cell in FIG. 1A, in accordance with an embodiment of the disclosure. FIG. 1C illustrates a cross-sectional view along line Y-Y′ of the pixel cell in FIG. 1A, in accordance with an embodiment of the disclosure. FIG. 1D illustrates a schematic for readout of the pixel cell in FIG. 1A, in accordance with an embodiment of the disclosure. FIG. 1E illustrates a timing diagram for readout of the pixel cell in FIG. 1A operating in a low conversion gain mode and a high conversion gain mode, in accordance with embodiments of the disclosure. FIG. 1F illustrates a potential diagram for the pixel cell of FIG. 1A operating in a low conversion gain mode and a high conversion gain mode, in accordance with embodiments of the disclosure. FIG. 2A illustrates a plan view of a pixel cell included in an image sensor with two multi-gate transfer transistors, in accordance with an embodiment of the disclosure. FIG. 2B illustrates a schematic for readout of the pixel cell in FIG. 2A, in accordance with an embodiment of the disclosure. FIG. 2C illustrates a schematic for readout of the pixel cell in FIG. 2A when the pixel cell includes a dual conversion gain transistor, in accordance with an embodiment of the disclosure. FIG. 2D illustrates a plan view of a pixel cell included in an image sensor with two multi-gate transfer transistors, in accordance with an embodiment of the disclosure. FIG. 3 illustrates a process for operating a pixel cell including a multi-gate transfer transistor, in accordance with an embodiment of the disclosure. FIG. 4 is a functional block diagram of an imaging system including a pixel cell with a multi-gate transfer transistor, in accordance with an embodiment of the disclosure. DETAILED DESCRIPTION Embodiments of an apparatus, system, and method each related to a pixel cell of an image sensor pixel cell with a multi-gate transfer transistor are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materi