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US-20260129995-A1 - INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF

US20260129995A1US 20260129995 A1US20260129995 A1US 20260129995A1US-20260129995-A1

Abstract

A device includes a first tier which includes a first substrate, a first device disposed at a side of the first substrate, a first isolation structure surrounding the first device, a second isolation structure disposed between the first isolation structure and a sidewall of the first substrate, a through substrate via (TSV) extending between the side and an opposing side of the first substrate, and a first bonding structure disposed over the side of the first substrate and electrically coupled to the first device. The TSV is laterally separated from the first isolation structure by the second isolation structure.

Inventors

  • Min-Feng KAO
  • Jen-Cheng Liu
  • Hsiu-Yun YEH

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date
20260507
Application Date
20241105

Claims (20)

  1. 1 . A device, comprising: a first tier comprising: a first substrate comprising a first side, a second side opposite to the first side, and a sidewall connected to the first side and the second side; a first device disposed at the first side of the first substrate; a first isolation structure surrounding the first device; a second isolation structure disposed between the first isolation structure and the sidewall of the first substrate; a through substrate via (TSV) extending between the first side and the second side of the first substrate, the TSV being laterally separated from the first isolation structure by the second isolation structure; and a first bonding structure disposed over the first side of the first substrate and electrically coupled to the first device.
  2. 2 . The device of claim 1 , wherein the TSV penetrates through the second isolation structure.
  3. 3 . The device of claim 1 , wherein the first tier further comprises: an interconnect structure disposed over the first side of the first substrate and electrically coupled to the first device, wherein the TSV comprises a first portion laterally connected to the first substrate, a second portion laterally connected to the interconnect structure, and a third portion connected to the first and second portions and laterally connected to the second isolation structure.
  4. 4 . The device of claim 1 , wherein the TSV is encircled by and laterally spaced apart from the second isolation structure.
  5. 5 . The device of claim 4 , wherein a portion of the first substrate laterally separates the TSV from the second isolation structure, and the portion of the first substrate comprises a lateral thickness on a sidewall of the TSV increases in a direction from the first side of the first substrate toward the second side of the first substrate.
  6. 6 . The device of claim 1 , wherein the first tier further comprises: a dummy device surrounded by the second isolation structure, the TSV being laterally separated from the first device by the dummy device and the second isolation structure, and the dummy device being electrically floating in the first tier.
  7. 7 . The device of claim 1 , wherein the first tier further comprises: a third isolation structure laterally interposed between the first and second isolation structures, the third isolation structure being tapered in the direction from the first side of the first substrate toward the second side of the first substrate.
  8. 8 . The device of claim 1 , further comprising: a second tier bonded to the first tier, the second tier comprising: a second substrate comprising a first side and a second side opposite to the first side; a second device disposed at the first side of the second substrate; a third bonding structure disposed over the first side of the second substrate and electrically coupled to the first device, the third bonding structure being bonded to a second bonding structure of the first tier, wherein the second bonding structure of the first tier is disposed below the second side of the first substrate and electrically coupled to the first device through the TSV.
  9. 9 . The device of claim 8 , wherein each of the second and third bonding structures comprises a bonding dielectric layer and bonding conductors laterally covered by the bonding dielectric layer, and a bonding surface of each of the second and third bonding structures is substantially flat.
  10. 10 . The device of claim 8 , further comprising: a third tier bonded to the first tier, the third tier comprising: a third substrate comprising a first side and a second side opposite to the first side; a third device disposed at the first side of the third substrate; an image sensing element disposed within the third substrate and coupled to the third device; a fourth bonding structure disposed over the first side of the third substrate and electrically coupled to the third device, the fourth bonding structure being bonded to the first bonding structure of the first tier.
  11. 11 . The device of claim 10 , wherein the third tier comprises pixel sensors arranged in an array and comprising the image sensing element in the third substrate.
  12. 12 . A device, comprising: a first tier comprising: a first substrate; an active device region disposed at a front side of the first substrate; a first isolation structure encircling the active device region; a second isolation structure disposed between the first isolation structure and an edge of the first substrate; a through substrate via (TSV) penetrating through the first substrate, the TSV and the second isolation structure being tapered in opposing directions; and a front-side bonding structure disposed over the front side of the first substrate and electrically coupled to the TSV and the active device region.
  13. 13 . The device of claim 12 , wherein the second isolation structure is a close loop encircling the TSV in a top view.
  14. 14 . The device of claim 12 , wherein the TSV penetrates through the second isolation structure, and the second isolation structure extends further than the first isolation structure.
  15. 15 . The device of claim 12 , wherein the first tier further comprises: a third isolation structure laterally between the first and second isolation structures and comprises a different top-view shape than the first isolation structure.
  16. 16 . The device of claim 12 , further comprising: a second tier stacked upon and bonded to the first tier, the second tier comprising: a second substrate comprising a first side and a second side opposite to the first side; image sensing elements disposed between the first and second sides of the second substrate; light filter regions disposed over the second side of the second substrate and directly over the image sensing elements; and a bonding structure disposed below the first side of the second substrate and bonded to the front-side bonding structure of the first tier.
  17. 17 . A manufacturing method of a device, comprising: providing a first tier comprising: forming a first isolation structure, a second isolation structure, and a first device at a first side of a first substrate, wherein the first isolation structure surrounds the first device, and the second isolation structure is between the first isolation structure and a sidewall of the first substrate connected to the first side of the first substrate; forming a first bonding structure over the first side of the first substrate; and forming a through substrate via (TSV) to pass through the first substrate, wherein the TSV is laterally separated from the first isolation structure by the second isolation structure.
  18. 18 . The manufacturing method of claim 17 , wherein the first and second isolation structures are formed at a same step.
  19. 19 . The manufacturing method of claim 17 , wherein providing the first tier further comprises: performing a planarization process on the first bonding structure, wherein the first bonding structure comprises a bonding dielectric layer and bonding conductors laterally covered by the bonding dielectric layer.
  20. 20 . The manufacturing method of claim 17 , further comprising: providing a second tier, wherein the second tier comprises: a second substrate comprising a first side and a second side opposite to the first side; image sensing elements formed between the first and second sides of the second substrate; light filter regions formed over the second side of the second substrate and corresponding to the image sensing elements; and a second bonding structure formed over the first side of the second substrate; and bonding the second tier to the first tier, where the second bonding structure of the second tier is bonded to the first bonding structure of the first tier.

Description

BACKGROUND Many modern-day electronic devices (e.g., smartphones, digital cameras, biomedical imaging devices, automotive imaging devices, etc.) include image sensors. The image sensors include one or more photodetectors configured to absorb incident radiation and output electrical signals corresponding to the incident radiation. Image sensors may include stacked dies to decrease a footprint of each pixel and increase device density. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a schematic cross-sectional view illustrating a first integrated circuit (IC) tier, in accordance with some embodiments. FIGS. 2A-2C are schematic cross-sectional views of various stages of a second IC tier, in accordance with some embodiments. FIGS. 3A-3D are schematic cross-sectional views of variations of a second IC tier, in accordance with some embodiments. FIG. 4 is a schematic cross-sectional view illustrating a third IC tier, in accordance with some embodiments. FIG. 5 is a schematic cross-sectional view illustrating a bonded structure including the first IC tier, the second IC tier, and the third IC tier, in accordance with some embodiments. FIG. 6 is a schematic cross-sectional view illustrating a stacked IC device, in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs. Formation of 3-dimensional IC (3DIC) by using through substrate vias (TSVs) to facilitate die stacking has contributed to the increase in integration density. However, the implementation of the TSVs to form 3DIC may cause stress being distributed on active regions near the TSVs during the fabrication process, thereby affecting the performance of active devices. It is important to reduce the effect of the TSVs on neighboring active devices. Embodiments will be described with respect to specific embodiments in which a stacked IC device may include multiple IC tiers stacked upon and bonded to one another. The TSVs in the middle IC tier of the stacked IC device may penetrate through an isolation structure and/or be laterally surrounded by an isolation structure. The isolation structure associated with the TSVs may function as a stress-relief structure, thereby reducing the stress on the adjacent active devices. The stacked IC device may be implemented as a complementary metal-oxide semiconductor (CMOS) image sensor device, a memory device (e.g., a