US-20260129998-A1 - Silicon Wafer-Scale System, Repair Method Thereof, and Electronic Device

Abstract

A silicon wafer-scale system includes an optical interconnect layer between a processor layer and a memory layer. A single processor chip at the processor layer can access data of any memory chip at the memory layer by using an optical signal through an optoelectronic conversion module. Data exchange can be performed between processor chips at the processor layer by using an optical signal through an optoelectronic conversion module.

Inventors

• WENQIANG ZHANG
• Guangfan Jiao
• Weiliang Jing
• Zhengbo WANG
• Heng Liao

Assignees

• HUAWEI TECHNOLOGIES CO., LTD.

Dates

Publication Date

20260507

Application Date

20241122

Priority Date

20220526

Claims (20)

1. 1 . A silicon wafer-scale system comprising: a processor layer comprising a plurality of processor chips; a memory layer comprising a plurality of memory chips; and an optical interconnect layer comprising an optical waveguide and a plurality of groups of optoelectronic converters, wherein each of the groups of optoelectronic converters comprises a photoelectric modulator and a photodetector, wherein the photoelectric modulator and the photodetector are separately coupled to the optical waveguide, wherein each processor chip in the plurality of processor chips is electrically connected to at least one of the groups of optoelectronic converters, and wherein each memory chip in the plurality of memory chips is electrically connected to at least one of the groups of optoelectronic converters.
2. 2 . The silicon wafer-scale system of claim 1 , wherein at least one processor chip in the plurality of processor chips is electrically connected to a vertically-stacked memory chip through a through-silicon via in the optical interconnect layer.
3. 3 . The silicon wafer-scale system of claim 1 , wherein each of the groups of optoelectronic converters is electrically connected to only one of the processor chips or one of the memory chips.
4. 4 . The silicon wafer-scale system of claim 3 , wherein each processor chip in the plurality of processor chips is electrically connected to a first group of the groups of optoelectronic converters, and wherein the first group is configured to bear conversion between optical signals of a single wavelength or a plurality of wavelengths and electrical signals.
5. 5 . The silicon wafer-scale system of claim 3 , wherein each memory chip in the plurality of memory chips is electrically connected to a first group of the groups of optoelectronic converters, and wherein the first group is configured to bear conversion between optical signals of a single wavelength or a plurality of wavelengths and electrical signals.
6. 6 . The silicon wafer-scale system of claim 3 , further comprising: a first drive circuit coupled to the photoelectric modulator, wherein the photoelectric modulator is electrically connected to a first processor chip of the plurality of processor chips or to a first memory chip of the plurality of memory chips through the first drive circuit; and a second drive circuit coupled to the photodetector, wherein the photodetector is electrically connected to a second processor chip of the plurality of processor chips or to a second memory chip of the plurality of memory chips through the second drive circuit.
7. 7 . The silicon wafer-scale system of claim 6 , wherein both the first drive circuit and the second drive circuit are integrated in the optical interconnect layer, wherein the first drive circuit is electrically connected to the photoelectric modulator through a first metal interconnect line, and wherein the second drive circuit is electrically connected to the photodetector through a second metal interconnect line.
8. 8 . The silicon wafer-scale system of claim 6 , wherein the first drive circuit and the second drive circuit are integrated in the processor layer, wherein the first drive circuit is electrically connected to the first processor chip through first metal interconnect lines, and wherein the second drive circuit is electrically connected to the second processor chip through second metal interconnect lines.
9. 9 . The silicon wafer-scale system of claim 6 , wherein the first drive circuit and the second drive circuit are integrated in the memory layer, wherein the first drive circuit is electrically connected to the first memory chip through first metal interconnect lines, and wherein the second drive circuit is electrically connected to the second memory chip through second metal interconnect lines.
10. 10 . The silicon wafer-scale system of claim 1 , wherein the optical interconnect layer further comprises: a plurality of optical waveguides comprising a first optical waveguide extending in a first direction and a second optical waveguide extending in a second direction, wherein the first direction and the second direction are crossed; and an optical switch disposed at a cross location of the first optical waveguide and the second optical waveguide and configured to control transmission of an optical signal to be switched between the first optical waveguide and the second optical waveguide.
11. 11 . The silicon wafer-scale system of claim 1 , wherein the optical interconnect layer further comprises at least one group of input/output components, wherein each of the at least one group of input/output components comprises an optical coupler and an optical fiber, and wherein the optical fiber is coupled to the optical waveguide through the optical coupler.
12. 12 . The silicon wafer-scale system of claim 1 , wherein the plurality of processor chips comprises a first processor chip and a second processor chip adjacent to the first processor chip, and wherein the first processor chip and the second processor chip are electrically connected through a metal interconnect line.
13. 13 . The silicon wafer-scale system of claim 1 , wherein the plurality of memory chips comprises a first memory chip and a second memory chip adjacent to the first memory chip, and wherein the first memory chip and the second memory chip are electrically connected through a metal interconnect line.
14. 14 . The silicon wafer-scale system of claim 1 , wherein both the processor layer is electrically connected to the optical interconnect layer and the optical interconnect layer is electrically connected to the memory layer in a hybrid bonding manner.
15. 15 . The silicon wafer-scale system of claim 1 , further comprising: an upper side; a lower side; and a heat dissipater located on at least one of the upper side or the lower side.
16. 16 . The silicon wafer-scale system of claim 1 , further comprising: an upper side; a lower side; and a power supply located on at least one of the upper side or the lower side.
17. 17 . An electronic device comprising: a silicon wafer-scale system, comprising: a processor layer comprising a plurality of processor chips; a memory layer comprising a plurality of memory chips; and an optical interconnect layer comprising an optical waveguide and a plurality of groups of optoelectronic converters, wherein each of the groups of optoelectronic converters comprises a photoelectric modulator and a photodetector, wherein the photoelectric modulator and the photodetector are separately coupled to the optical waveguide, wherein each processor chip in the plurality of processor chips is electrically connected to at least one group of optoelectronic converters, and wherein each memory chip in the plurality of memory chips is electrically connected to at least one group of optoelectronic converters; and a circuit board electrically connected to the silicon wafer-scale system.
18. 18 . The electronic device of claim 17 , wherein each of the groups of optoelectronic converters is electrically connected to only one of the processor chips or one of the memory chips.
19. 19 . The electronic device of claim 17 , wherein the optical interconnect layer comprises: a plurality of optical waveguides comprising a first optical waveguide extending in a first direction and a second optical waveguide extending in a second direction, wherein the first direction and the second direction are crossed; and an optical switch disposed at a cross location of the first optical waveguide and the second optical waveguide, and configured to control transmission of an optical signal to be switched between the first optical waveguide and the second optical waveguide.
20. 20 . A method for repairing a silicon wafer-scale system and comprising: separately testing a processor layer, a memory layer, and an optical interconnect layer of the silicon wafer-scale system to determine a damaged processor chip, a damaged memory chip, or a damaged optoelectronic converter; and shielding the damaged processor chip, the damaged memory chip, or the damaged optoelectronic converter during compiling of a program.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This is a continuation of International Patent Application No. PCT/CN2023/071808 filed on Jan. 11, 2023, which claims priority to Chinese Patent Application No. 202210584869.X filed on May 26, 2022. The disclosures of the aforementioned applications are hereby incorporated by reference in their entireties. TECHNICAL FIELD This disclosure relates to the field of semiconductor technologies, and in particular, to a silicon wafer-scale system, a repair method thereof, and an electronic device. BACKGROUND In disclosure of high-performance computing and artificial intelligence, a large-scale computing task requires a large quantity of processors to perform parallel computing, for example, a central processing unit (CPU), a graphics processing unit (GPU), or a neural network processing unit (NPU). In a parallel computing process of a plurality of processors, a large amount of data needs to be exchanged between the processors. In addition, for the large-scale computing task, access of a large amount of data exists between a processor and a memory. Currently, a single processor and a single memory are usually separately packaged, and communication between processors or between a processor and a memory requires a long connection line. Such a long connection line causes a limited bandwidth and a large delay of communication. This becomes a bottleneck for the large-scale computing task. To improve a bandwidth between processors and a capacity of a memory that can be accessed by a processor, a plurality of three-dimensional (3D) heterogeneous integrated silicon wafer-scale/wafer-scale systems and packaging solutions are proposed. SUMMARY This disclosure provides a silicon wafer-scale system, a repair method thereof, and an electronic device, to improve a bandwidth between processors and a capacity of a memory that can be accessed by a processor. According to a first aspect, this disclosure provides a silicon wafer-scale system, including: a processor layer, an optical interconnect layer, and a memory layer that are sequentially stacked. The processor layer may include a plurality of processor chips. One or more processor dies may be integrated into the processor chip. Alternatively, each processor chip may be an uncut wafer. A plurality of processor chips on a same plane form one processor layer. There may be one or more memory layers. The plurality of memory layers may be electrically interconnected (for example, electrically connected in a hybrid bonding manner), or may be optically interconnected (for example, one optical interconnect layer is added between two memory layers). Each memory layer may include a plurality of memory chips. One or more memory dies may be integrated into each memory chip. Alternatively, each memory chip may be an uncut wafer. A plurality of memory chips on a same plane form one memory layer. The optical interconnect layer may include a plurality of groups of optoelectronic conversion modules and an optical waveguide. The plurality of groups of optoelectronic conversion modules in the optical interconnect layer may be independently packaged, or may be packaged on an uncut wafer. Each group of optoelectronic conversion modules may include a photoelectric modulator and a photodetector. The photoelectric modulator and the photodetector are separately coupled to the optical waveguide. In other words, optoelectronic conversion modules are connected through the optical waveguide. Each processor chip may be electrically connected to at least one group of optoelectronic conversion modules. Each memory chip may be electrically connected to at least one group of optoelectronic conversion modules. The photoelectric modulator is configured to: convert an electrical signal from an electrically connected memory chip or an electrically connected processor chip into an optical signal, to implement conversion from electrical data to optical data; and import the optical signal into the optical waveguide for transmission. The photoelectric modulator may include a plurality of types of photoelectric transistors, corresponding control circuits, and other components. The photodetector is configured to: convert an optical signal transmitted in the optical waveguide into an electrical signal, to implement conversion from optical data to electrical data; and transmit the electrical signal to an electrically connected memory chip or an electrically connected processor chip. The photodetector may include a component that converts an optical signal into an electrical signal, such as a photodiode, a photomultiplier tube, or a photoconductive detector; and may further include a corresponding control circuit and the like. According to the silicon wafer-scale system provided in this embodiment of this disclosure, by adding the optical interconnect layer between the processor layer and the memory layer, a single processor chip at the processor layer can communicate with any memory chi