US-20260130065-A1 - DISPLAY PANEL AND ELECTRONIC DEVICE INCLUDING THE SAME

US20260130065A1US 20260130065 A1US20260130065 A1US 20260130065A1US-20260130065-A1

Abstract

A display panel includes a base substrate, a semiconductor pattern, an insulating layer, a gate pattern, an inter-insulating layer, a source-drain pattern, a via layer, and a light-emitting diode. The base substrate includes a first region and a second region including a bending region which is bendable, a cover region extending from one side of the bending region and surrounds the first region, and a pad region extending from an opposite side of the bending region. The semiconductor pattern on the first region includes a semiconductor material. The insulating layer on the base substrate covers the semiconductor pattern. The gate pattern on the gate insulating layer at least partially overlaps the semiconductor pattern. The insulating layer covers the gate pattern. First crack-prevention openings and second crack-prevention openings are defined in the insulating layer. The number of the first crack-prevention openings is different from the number of the second crack-prevention openings.

Inventors

Sun-Kyo Jung
Hosung Song
Sung-min Cho

Assignees

SAMSUNG DISPLAY CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20250602
Priority Date: 20241101

Claims (20)

1 . A display panel comprising: a base substrate including: a first region; and a second region comprising: a bending region which is bendable; a cover region extending from one side of the bending region and surrounding the first region; and a pad region extending from an opposite side of the bending region opposite to the one side of the bending region; a semiconductor pattern disposed on the first region and comprising a semiconductor material; a gate insulating layer disposed on the base substrate and covering the semiconductor pattern; a gate pattern disposed on the gate insulating layer and comprising at least a portion overlapping the semiconductor pattern; an inter-insulating layer covering the gate pattern; a source-drain pattern disposed on the inter-insulating layer and comprising at least a portion electrically connected to the semiconductor pattern; a via layer covering the source-drain pattern; and a light-emitting diode disposed on the via layer, wherein a plurality of first crack-prevention openings, each extending along an outer edge of the cover region, is defined in a portion of the inter-insulating layer overlapping the cover region, a plurality of second crack-prevention openings, each extending along an outer edge of the pad region, is defined in a portion of the inter-insulating layer overlapping the pad region, and a number of the plurality of first crack-prevention openings and a number of the plurality of second crack-prevention openings are different from each other.
2 . The display panel of claim 1 , wherein the number of the plurality of second crack-prevention openings is greater than the number of the plurality of first crack-prevention openings.
3 . The display panel of claim 2 , wherein at least one of a plurality of third crack-prevention openings and a plurality of fourth crack-prevention openings is defined in the gate insulating layer, wherein the plurality of third crack-prevention openings overlaps the plurality of first crack-prevention openings, respectively, and the plurality of fourth crack-prevention openings overlaps the plurality of second crack-prevention openings, respectively.
4 . The display panel of claim 3 , further comprising: a plurality of pads disposed on the pad region; an electrical component overlapping the plurality of pads; and a plurality of spider wirings, each extending from the plurality of pads and configured to transfer signals provided by the electrical component to at least one of the source-drain pattern and the gate pattern, wherein the plurality of second crack-prevention openings is defined between the plurality of spider wirings and the outer edge of the pad region.
5 . The display panel of claim 4 , wherein the plurality of second crack-prevention openings is spaced apart from the plurality of first crack-prevention openings across the bending region in a plan view.
6 . The display panel of claim 4 , wherein, when the bending region is bent, the plurality of second crack-prevention openings overlaps at least one of the first region and the cover region.
7 . The display panel of claim 4 , wherein the base substrate comprises: a first base layer comprising an organic material; a second base layer disposed on the first base layer; and a third base layer disposed on the second base layer and comprising an organic material, at least one of a plurality of fifth crack-prevention openings and a plurality of sixth crack-prevention openings is defined in second base layer, the plurality of fifth crack-prevention openings overlaps the plurality of first crack-prevention openings, respectively, and the plurality of sixth crack-prevention openings overlaps the plurality of second crack-prevention openings, respectively.
8 . The display panel of claim 4 , wherein a shape formed by projecting each of the plurality of second crack-prevention openings onto the base substrate comprises at least one of a line shape, a curve shape, and a zigzag shape.
9 . The display panel of claim 4 , further comprising a functional layer disposed between the base substrate and the semiconductor pattern, wherein at least one of a plurality of seventh crack-prevention openings and a plurality of eighth crack-prevention openings is defined in the functional layer, the plurality of seventh crack-prevention openings overlaps the plurality of first crack-prevention openings, respectively, and the plurality of eighth crack-prevention openings overlaps the plurality of second crack-prevention openings, respectively.
10 . A display panel comprising: a base substrate including: a first region; and a second region comprising: a bending region which is bendable; a cover region extending from one side of the bending region and surrounding the first region; and a pad region extending from an opposite side of the bending region opposite to the one side of the bending region; a semiconductor pattern disposed on the first region and comprising a semiconductor material; a gate insulating layer disposed on the base substrate and covering the semiconductor pattern; a gate pattern disposed on the gate insulating layer and comprising at least a portion overlapping the semiconductor pattern; an inter-insulating layer covering the gate pattern and comprising: a plurality of first protruding members spaced apart from each other on the cover region; and a plurality of second protruding members spaced apart from each other on the pad region, a source-drain pattern disposed on the inter-insulating layer comprising at least a portion electrically connected to the semiconductor pattern; a via layer covering the source-drain pattern; and a light-emitting diode disposed on the via layer, wherein each of the first protruding members extends along at least a portion of an outer boundary of the cover region, each of the second protruding members extends along at least a portion of an outer boundary of the pad region, and a number of the first protruding members and a number of the second protruding members are different from each other.
11 . The display panel of claim 10 , wherein the number of the second protruding members is greater than the number of the first protruding members.
12 . The display panel of claim 11 , wherein the gate insulating layer comprises at least one of a plurality of third protruding members overlapping, respectively, the plurality of first protruding members and a plurality of fourth protruding members overlapping, respectively, the plurality of second protruding members.
13 . The display panel of claim 12 , further comprising: a plurality of pads disposed on the pad region; an electrical component electrically connected to the plurality of pads; and a plurality of spider wirings, each extending from the plurality of pads and configured to transfer signals provided by the electrical component to at least one of the source-drain pattern and the gate pattern, wherein the plurality of second protruding members is arranged between the plurality of spider wirings and an outer edge of the pad region.
14 . The display panel of claim 13 , wherein the plurality of second protruding members is spaced apart from the plurality of first protruding members across the bending region in a plan view.
15 . The display panel of claim 13 , wherein, when the bending region is bent, the plurality of second protruding members overlaps at least one of the first region and the cover region.
16 . The display panel of claim 13 , wherein the base substrate comprises: a first base layer comprising an organic material; a second base layer disposed on the first base layer and comprising at least one of a plurality of fifth protruding members overlapping, respectively, the plurality of first protruding members and a plurality of sixth protruding members overlapping, respectively, the plurality of second protruding members; and a third base layer disposed on the second base layer and comprising an organic material.
17 . The display panel of claim 13 , wherein a shape formed by projecting each of the plurality of second protruding members onto the base substrate comprises at least one of a line shape, a curve shape, and a zigzag shape.
18 . The display panel of claim 13 , further comprising a functional layer disposed between the base substrate and the semiconductor pattern, wherein the functional layer comprises at least one of a plurality of seventh protruding members overlapping, respectively, the plurality of first protruding members and a plurality of eighth protruding members overlapping, respectively, the plurality of second protruding members.
19 . An electronic device comprising: a display panel comprising: a base substrate including: a first region; and a second region comprising: a bending region which is bendable; a cover region extending from one side of the bending region and surrounding the first region; and a pad region extending from an opposite side of the bending region opposite to the one side of the bending region; a semiconductor pattern disposed on the first region and comprising a semiconductor material; a gate insulating layer disposed on the base substrate and covering the semiconductor pattern; a gate pattern disposed on the gate insulating layer including at least a portion overlapping the semiconductor pattern; an inter-insulating layer covering the gate pattern and comprising: a plurality of first protruding members spaced apart from each other on the cover region; and a plurality of second protruding members spaced apart from each other on the pad region; a source-drain pattern disposed on the inter-insulating layer and comprising at least a portion electrically connected to the semiconductor pattern; a via layer covering the source-drain pattern; and a light-emitting diode disposed on the via layer, wherein each of the first protruding members extends along at least a portion of an outer boundary of the cover region, each of the second protruding members extends along at least a portion of an outer boundary of the pad region, and a number of the first protruding members and a number of the second protruding members are different from each other.
20 . The electronic device of claim 19 , wherein a plurality of first crack-prevention openings, each extending along an outer edge of the cover region, is defined in a portion of the inter-insulating layer overlapping the cover region, wherein a plurality of second crack-prevention openings, each extending along an outer edge of the pad region, is defined in a portion of the inter-insulating layer overlapping the pad region, wherein each of the plurality of first protruding members is disposed between two first crack-prevention openings next to each other among the plurality of first crack-prevention openings, and wherein each of the plurality of second protruding members is disposed between two second crack-prevention openings next to each other among the plurality of second crack-prevention openings.

Description

This application claims priority to Korean Patent Application No. 10-2024-0153833, filed on Nov. 1, 2024, and all the benefits accruing therefrom under 35 U.S.C. § 119, the content of which in its entirety is herein incorporated by reference. BACKGROUND 1. Field The disclosure relates to a display panel configured for preventing defects caused by crack propagation, and an electronic device including the same. 2. Description of the Related Art A display panel and an electronic device containing the display panel typically include a plurality of light-emitting diodes to provide images to users. Additionally, wiring for controlling the plurality of light-emitting diodes is arranged on the display panel. SUMMARY During the usage of an electronic device by the user, various forms of impact may be exerted to the display panel. Consequently, cracks may occur in the display panel, and if the cracks propagate to the aforementioned wiring, the wiring may become exposed externally. The exposed wiring is susceptible to corrosion, and such corrosion may lead to malfunction of the display panel. Particularly, when cracks occur in areas where more wiring is concentrated, the likelihood of failure due to crack propagation increases. The vulnerability of the display panel to crack propagation-induced failure may vary depending on the specific regions of the display panel. A feature of the disclosure is to provide a display panel and an electronic device having the same, capable of effectively preventing defects caused by crack propagation by designing crack dams in a differentiated manner depending on the region. A display panel in an embodiment of the disclosure may include a base substrate, a semiconductor pattern, a gate insulating layer, a gate pattern, an inter-insulating layer, a source-drain pattern, a via layer, and a light-emitting diode. The base substrate may have a first region and a second region defined therein. The second region may include a bending region, a cover region, and a pad region. The bending region may be bendable. The cover region may extend from one side of the bending region and surround the first region. The pad region may extend from the opposite side of the bending region. The semiconductor pattern may be disposed on the first region and may include a semiconductor material. The gate insulating layer may be disposed on the base substrate and may cover the semiconductor pattern. The gate pattern may be disposed on the gate insulating layer, with at least a portion thereof overlapping the semiconductor pattern. The inter-insulating layer may cover the gate pattern. A plurality of first crack-prevention openings defined in a portion of the inter-insulating layer overlapping the cover region and a plurality of second crack-prevention openings defined in a portion of the inter-insulating layer overlapping the pad region. Each of the plurality of first crack-prevention openings may extend along an outer edge of the cover region, and each of the plurality of second crack-prevention openings may extend along an outer edge of the pad region. The number of the plurality of first crack-prevention openings and the number of the plurality of second crack-prevention openings may differ from each other. The source-drain pattern may be disposed on the inter-insulating layer, with at least a portion thereof electrically connected to the semiconductor pattern. The via layer may cover the source-drain pattern, and the light-emitting diode may be disposed on the via layer. In an embodiment of the disclosure, the number of the plurality of second crack-prevention openings may be greater than the number of the plurality of first crack-prevention openings. In an embodiment of the disclosure, at least one of a plurality of third crack-prevention openings and a plurality of fourth crack-prevention openings may be defined in the gate insulating layer. The plurality of third crack-prevention openings may overlap the first crack-prevention openings, respectively. The plurality of fourth crack-prevention openings may overlap the second crack-prevention openings, respectively. A display panel in an embodiment of the disclosure may further include a plurality of pads, an electrical component, and a plurality of spider wirings. The plurality of pads may be arranged on the pad region. The electrical component may overlap the plurality of pads. Each of the plurality of spider wirings may extend, respectively, from the pads and transfer signals from the electrical component to at least one of the source-drain pattern and the gate pattern. The plurality of second crack-prevention openings may be defined between the plurality of spider wirings and the outer edge of the pad region. In an embodiment of the disclosure, the plurality of second crack-prevention openings may be spaced apart from the plurality of first crack-prevention openings across the bending region in a plan view. In an embodiment of the disclosure, when the bend