US-20260130082-A1 - DISPLAY PANEL AND DISPLAY DEVICE

Abstract

Provided is a display panel. The display panel includes a base substrate, a plurality of pixel units, and a plurality of gate signal lines. The base substrate has a display region and a periphery region surrounding the display region, wherein the display region includes a plurality of pixel light-emitting regions and a plurality of transparent regions, the plurality of transparent regions including at least one target transparent region arranged in a first direction. The plurality of pixel units, disposed on the base substrate and in the plurality of pixel light-emitting regions. The plurality of gate signal lines are arranged in a second direction.

Inventors

• Can Yuan
• Yongqian Li
• Biao TIAN

Assignees

• HEFEI BOE JOINT TECHNOLOGY CO., LTD.
• BOE TECHNOLOGY GROUP CO., LTD.

Dates

Publication Date

20260507

Application Date

20240528

Priority Date

20240417

Claims (20)

1. 1 . A display panel, comprising: a base substrate, having a display region and a periphery region surrounding the display region, wherein the display region comprises a plurality of pixel light-emitting regions and a plurality of transparent regions, the plurality of transparent regions comprising at least one target transparent region arranged in a first direction; a plurality of pixel units, disposed on the base substrate and in the plurality of pixel light-emitting regions; and a plurality of gate signal lines, arranged in a second direction, wherein the second direction is intersected with the first direction, and each of the plurality of gate signal lines comprises a first section in the periphery region and a second section in the display region, wherein the second section comprises a body portion extending in the first direction and a bent portion connected to the body portion, the bent portion being disposed in the at least one target transparent region, and a path length of the bent portion being greater than a length of the at least one target transparent region in the first direction.
2. 2 . The display panel according to claim 1 , further comprising: a protection pattern and a first insulation layer between the protection pattern and the plurality of gate signal lines, wherein the protection pattern is disposed in the at least one target transparent region, an orthographic projection of the bent portion on the base substrate is on a side of an orthographic projection of the protection pattern on the base substrate, and the orthographic projection of the protection pattern on the base substrate is partially overlapped with the orthographic projection of the bent portion on the base substrate.
3. 3 . The display panel according to claim 2 , wherein the bent portion comprises a first bent portion, a second bent portion, and a third bent portion that are connected in sequence, and the plurality of gate signal lines form a plurality of signal line groups, each group of the plurality of signal line groups comprising two adjacent gate signal lines; wherein the first bent portion in each of the two adjacent gate signal lines is disposed in a side, away from the periphery region, of the protection pattern, and the third bent portion in each of the two adjacent gate signal lines is disposed in a side, close to the periphery region, of the protection pattern; and an orthographic projection of the second bent portion of a first gate signal line in the two adjacent gate signal lines on the base substrate is on a first side of the orthographic projection of the protection pattern on the base substrate and is partially overlapped with the orthographic projection of the protection pattern on the base substrate, and an orthographic projection of the second bent portion of a second gate signal line in the two adjacent gate signal lines on the base substrate is on a second side of the orthographic projection of the protection pattern on the base substrate and is partially overlapped with the orthographic projection of the protection pattern on the base substrate, wherein the first side and the second side are two sides, arranged in the second direction, of the orthographic projection of the protection pattern on the base substrate.
4. 4 . The display panel according to claim 3 , wherein orthographic projections of bent portions of the two gate signal lines on the base substrate surround the orthographic projection of the protection pattern on the base substrate.
5. 5 . The display panel according to claim 4 , wherein the bent portions of the two gate signal lines define a first annular region, a portion of the first gate signal line in one of the plurality of pixel light-emitting regions has a second annular region, and a portion of the second gate signal line in one of the plurality of pixel light-emitting regions has a third annular region; wherein an area of the first annular region is greater than an area of the second annular region and an area of the third annular region.
6. 6 . The display panel according to claim 5 , wherein the at least one target transparent region comprises a first target transparent region, wherein the first target transparent region is closer to the periphery region than the plurality of pixel light-emitting regions; wherein for the first annular region defined by the bent portions of the two gate signal lines in the first target transparent region, a distance between the first annular region and one of the plurality of pixel light-emitting regions is greater than a distance between the first annular region and the periphery region.
7. 7 . The display panel according to claim 6 , wherein the protection pattern is a stripe pattern extending in the second direction, and a length of the protection pattern in the second direction is greater than the distance between the first annular region in the first target transparent region and one of the plurality of pixel light-emitting regions.
8. 8 . The display panel according to claim 6 , wherein the at least one target transparent region further comprises a second target transparent region, wherein the second target transparent region is disposed between two adjacent pixel light-emitting regions in the plurality of pixel light-emitting regions; wherein for the first annular region defined by the bent portions of the two gate signal lines in the second target transparent region, distances between the second annular region and the two adjacent pixel light-emitting regions are equal.
9. 9 . The display panel according to claim 3 , wherein a first protrusion is arranged on a side, close to the protection pattern, of the second bent portion of the first gate signal line, wherein an orthographic projection of a first end portion of the protection pattern on the base substrate is overlapped with an orthographic projection of the first protrusion on the base substrate; and a second protrusion is arranged on a side, close to the protection pattern, of the second bent portion of the second gate signal line, wherein an orthographic projection of a second end portion of the protection pattern on the base substrate is overlapped with an orthographic projection of the second protrusion on the base substrate.
10. 10 . The display panel according to claim 9 , comprising: a pixel unit layer, wherein the pixel unit layer comprises the plurality of pixel units and a semiconductor layer between the base substrate and the first insulation layer, wherein the protection pattern is disposed in the semiconductor layer, and each of the first end portion and the second end portion of the protection pattern is made of a semiconductor material.
11. 11 . The display panel according to claim 2 , comprising: a pixel unit layer, wherein the pixel unit layer comprises the plurality of pixel units, and a gate layer, a second insulation layer, and a cathode layer that are stacked in a direction away from the base substrate in sequence; wherein the plurality of gate signal lines are disposed in the gate layer, an orthographic projection of the second insulation layer on the base substrate covers orthographic projections of the plurality of gate signal lines on the base substrate and the orthographic projection of the protection pattern on the base substrate.
12. 12 . The display panel according to claim 11 , wherein the second insulation layer comprises a material region containing an insulative material and a void region without any insulative material; wherein the material region is disposed in the plurality of pixel light-emitting regions, and an orthographic projection of the material region on the base substrate covers the orthographic projection of the protection pattern on the base substrate and the orthographic projections of the plurality of gate signal lines on the base substrate; and the void region is disposed on a side, away from the orthographic projection of the protection pattern on the base substrate, of the orthographic projections of the plurality of gate signal lines on the base substrate, disposed between the orthographic projections of the plurality of gate signal lines on the base substrate and the orthographic projection of the protection pattern on the base substrate, and disposed in other regions of the plurality of transparent regions than regions of the orthographic projections of the plurality of gate signal lines on the base substrate; or the second insulation layer at least comprises a first insulation sub-layer and a second insulation sub-layer that are stacked in the direction away from the base substrate in sequence, wherein a boundary of an orthographic projection of the first insulation sub-layer on the base substrate is not overlapped with a boundary of an orthographic projection of the second insulation sub-layer on the base substrate.
13. 13 . (canceled)
14. 14 . The display panel according to claim 1 , wherein each of the plurality of pixel light-emitting regions and the plurality of transparent regions is a stripe region extending in the second direction, the plurality of pixel light-emitting regions and the plurality of transparent regions are staggered in the first direction, the plurality of transparent regions comprise two target transparent regions, and the plurality of pixel light-emitting regions and other transparent regions in the plurality of transparent regions than the two target transparent regions are disposed between the two target transparent regions; and each of the plurality of gate signal lines comprises two bent portions, wherein one bent portion in the two bent portions is connected to an end of the body portion and is disposed in one target transparent region in the two target transparent regions, and another bent portion in the two bent portions is connected to another end of the body portion and is disposed in another target transparent region in the two target transparent regions.
15. 15 . The display panel according to claim 1 , wherein the plurality of pixel units are arranged in an array and comprise a plurality of first pixel unit groups arranged in the second direction, wherein each group of the plurality of first pixel unit groups comprises multiple pixel units arranged in the first direction, each of the plurality of gate signal lines is connected to the multiple pixel units in one group of the plurality of first pixel unit groups, and the multiple pixel units in the each group of the plurality of first pixel unit groups are connected to two gate signal lines in one group of a plurality of signal line groups formed by the plurality of gate signal lines.
16. 16 . The display panel according to claim 15 , wherein each of the plurality of pixel units comprise a first group of sub-pixels and a second group of sub-pixels that are arranged in the second direction, wherein the first group of sub-pixels comprises at least one sub-pixel, the second group of sub-pixels comprises at least one sub-pixel, and body portions of the two gate signal lines connected to the multiple pixel units in the each group of the plurality of first pixel unit groups are disposed between the first group of sub-pixels and the second group of sub-pixels.
17. 17 . The display panel according to claim 16 , wherein the body portion comprises a first primary path line and a plurality of first secondary path lines; wherein two ends of each of the plurality of first secondary path lines are connected to the first primary path line, the first primary path line is connected to the at least one sub-pixel in first groups of sub-pixels of the multiple pixel units in one group of the plurality of first pixel unit groups, and each of the plurality of first secondary path lines is connected to the at least one sub-pixel in the second group of sub-pixels of one of the multiple pixel units.
18. 18 . The display panel according to claim 17 , wherein the plurality of pixel units comprise a plurality of second pixel unit groups arranged in the first direction, wherein each of the plurality of second pixel unit groups comprises multiple pixel units arranged in the second direction; the display panel further comprises a plurality of first power lines corresponding to the plurality of second pixel unit groups, and a plurality of corresponding auxiliary electrode lines, wherein each of the plurality of first power lines comprises a primary power line and a plurality of branch power lines, the plurality of branch power lines being connected to the primary power line, and the primary power line being disposed on a side of a corresponding second pixel unit group; each of the plurality of first power lines is connected to sub-pixels in the multiple pixel units in one group of the plurality of second pixel unit groups, and each of the plurality of auxiliary electrode lines is disposed on another side of the corresponding second pixel unit group and is connected to a cathode layer in the multiple pixel units; and for the primary power line and one of the plurality of auxiliary electrode lines of one of the plurality of first power lines corresponding to one group of the plurality of second pixel unit groups, one of connection positions between the two ends of one of the plurality of first secondary path lines and the first primary path line is disposed on a side, away from the one of the plurality of auxiliary electrode lines, of the primary power line, and another of the connection positions between the two ends of one of the plurality of first secondary path lines and the first primary path line is disposed on a side, away from the primary power line, of the one of the plurality of auxiliary electrode lines.
19. 19 . The display panel according to claim 17 , wherein the plurality of pixel units comprise a plurality of second pixel unit groups arranged in the first direction, wherein each group of the plurality of second pixel unit groups comprises multiple pixel units arranged in the second direction; the display panel further comprises a plurality of first power lines corresponding to the plurality of second pixel unit groups, and a plurality of corresponding auxiliary electrode lines, wherein each of the plurality of first power lines comprises a primary power line and a plurality of branch power lines, the plurality of branch power lines being connected to the primary power line, and the primary power line being disposed on a side of a corresponding second pixel unit group; each of the plurality of first power lines is connected to the multiple pixel units in one group of the plurality of second pixel unit groups, and each of the plurality of auxiliary electrode lines is disposed on another side of the corresponding second pixel unit group and is connected to a cathode layer in the multiple pixel units; for the primary power line and one of the plurality of auxiliary electrode lines of one of the plurality of first power lines corresponding to one group of the plurality of second pixel unit groups, two connection positions between the two ends of one of the plurality of first secondary path lines and the first primary path line are disposed between the primary power line and the one of the plurality of auxiliary electrode lines; and the body portion further comprises a plurality of second secondary path lines and a plurality of third secondary path lines, wherein two ends of each of the plurality of second secondary path lines are connected to the first primary path line, and two connection positions between the two ends of each of the plurality of second secondary path lines and the first primary path line are disposed on two side of the primary power line; and two ends of each of the plurality of third secondary path lines are connected to the first primary path line, and two connection positions between the two ends of each of the plurality of third secondary path lines and the first primary path line are disposed on two side of the one of the plurality of auxiliary electrode lines.
20. 20 . The display panel according to claim 18 , wherein the first group of sub-pixels comprises a first sub-pixel and a second sub-pixel, and the second group of sub-pixels comprises a third sub-pixel and a fourth sub-pixel; and the display panel further comprises a plurality of data signal line groups corresponding to the plurality of second pixel unit groups, wherein each group of the plurality of data signal line groups comprises a plurality of data signal lines arranged in the first direction, a target data signal line in the plurality of data signal lines being disposed between the first sub-pixel and the second sub-pixel and between the third sub-pixel and the fourth sub-pixel, and being at least one data signal line in the plurality of data signal lines; and each of the plurality of branch power lines comprises a second primary path line and a fourth secondary path line, wherein two ends of the fourth secondary path line are connected to the second primary path line, and two connection positions between the two ends of the fourth secondary path line and the second primary path line are disposed on two sides of the target data signal line.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a U.S. national stage of international application No. PCT/CN 2024/095856, filed on May 28, 2024, which claims priority to Chinese Patent Application No. 202410465765.6, filed on Apr. 17, 2024 and entitled “DISPLAY PANEL AND DISPLAY DEVICE,” the disclosure of each is herein incorporated by reference in its entirety. TECHNICAL FIELD The present disclosure relates to the technical field of display, and in particular, relates to a display panel and a display device. BACKGROUND A display penal generally includes a plurality of pixel units arranged in an array in a display region of a base substrate, and gate signal lines (generally referred to as Gate traces) configured to supply gate drive signals to the plurality of pixel units. SUMMARY A display panel and a display device are provided in the present disclosure. The technical solutions are as follows. In some embodiments of the present disclosure, a display panel is provided. The display panel includes: a base substrate, having a display region and a periphery region surrounding the display region, wherein the display region includes a plurality of pixel light-emitting regions and a plurality of transparent regions, the plurality of transparent regions including at least one target transparent region arranged in a first direction;a plurality of pixel units, disposed on the base substrate and in the plurality of pixel light-emitting regions; anda plurality of gate signal lines, arranged in a second direction, wherein the second direction is intersected with the first direction, and each of the plurality of gate signal lines includes a first section in the periphery region and a second section in the display region, wherein the second section includes a body portion extending in the first direction and a bent portion connected to the body portion, the bent portion being disposed in the at least one target transparent region, and a path length of the bent portion being greater than a length of the at least one target transparent region in the first direction. In some embodiments, the display panel further includes: a protection pattern and a first insulation layer between the protection pattern and the plurality of gate signal lines, wherein the protection pattern is disposed in the at least one target transparent region, an orthographic projection of the bent portion on the base substrate is on a side of an orthographic projection of the protection pattern on the base substrate, and the orthographic projection of the protection pattern on the base substrate is partially overlapped with the orthographic projection of the bent portion on the base substrate. In some embodiments, the bent portion includes a first bent portion, a second bent portion, and a third bent portion that are connected in sequence, and the plurality of gate signal lines form a plurality of signal line groups, each group of the plurality of signal line groups including two adjacent gate signal lines; wherein the first bent portion in each of the two adjacent gate signal lines is disposed in a side, away from the periphery region, of the protection pattern, and the third bent portion in each of the two adjacent gate signal lines is disposed in a side, close to the periphery region, of the protection pattern; andan orthographic projection of the second bent portion of a first gate signal line in the two adjacent gate signal lines on the base substrate is on a first side of the orthographic projection of the protection pattern on the base substrate and is partially overlapped with the orthographic projection of the protection pattern on the base substrate, and an orthographic projection of the second bent portion of a second gate signal line in the two adjacent gate signal lines on the base substrate is on a second side of the orthographic projection of the protection pattern on the base substrate and is partially overlapped with the orthographic projection of the protection pattern on the base substrate, wherein the first side and the second side are two sides, arranged in the second direction, of the orthographic projection of the protection pattern on the base substrate. In some embodiments, orthographic projections of bent portions of the two gate signal lines on the base substrate surround the orthographic projection of the protection pattern on the base substrate. In some embodiments, the bent portions of the two gate signal lines define a first annular region, a portion of the first gate signal line in one of the plurality of pixel light-emitting regions has a second annular region, and a portion of the second gate signal line in one of the plurality of pixel light-emitting regions has a third annular region;wherein an area of the first annular region is greater than an area of the second annular region and an area of the third annular region. In some embodiments, the at least one target transparent region include a first target t