US-20260130089-A1 - DISPLAY PANEL AND ELECTRONIC APPARATUS INCLUDING THE SAME

Abstract

A display panel includes a pixel circuit set including a first pixel circuit, a second pixel circuit, and a third pixel circuit, a first pixel electrode overlapping the first pixel circuit in a plan view, a second pixel electrode overlapping the second pixel circuit in a plan view, a third pixel electrode overlapping the third pixel circuit in a plan view, and a connection electrode arranged below the first pixel electrode, the second pixel electrode, and the third pixel electrode. In a plan view, an end of the connection electrode overlaps the first pixel electrode, and another end of the connection electrode overlaps the second pixel electrode.

Inventors

• Hyuk Kim
• Seungsoo Baek
• Boyong Chung
• JongHee KIM

Assignees

• SAMSUNG DISPLAY CO., LTD.

Dates

Publication Date

20260507

Application Date

20250725

Priority Date

20241101

Claims (20)

1. 1 . A display panel comprising: a pixel circuit set including a first pixel circuit, a second pixel circuit, and a third pixel circuit; a first pixel electrode overlapping the first pixel circuit in a plan view; a second pixel electrode overlapping the second pixel circuit in a plan view; a third pixel electrode overlapping the third pixel circuit in a plan view; and a connection electrode arranged below the first pixel electrode, the second pixel electrode, and the third pixel electrode, wherein, in a plan view, an end of the connection electrode overlaps the first pixel electrode, and another end of the connection electrode overlaps the second pixel electrode.
2. 2 . The display panel of claim 1 , further comprising: a bank layer arranged over the first pixel electrode, the second pixel electrode, and the third pixel electrode, the bank layer including a first opening overlapping the first pixel electrode, a second opening overlapping the second pixel electrode, and a third opening overlapping the third pixel electrode in a plan view.
3. 3 . The display panel of claim 2 , wherein the first opening is larger than the second opening and the third opening in a plan view, and the second opening is smaller than the third opening in a plan view.
4. 4 . The display panel of claim 2 , wherein the second pixel electrode includes a first portion and a second portion, the first portion overlapping the second opening in a plan view, and the second portion being spaced apart from the first portion with a gap between the first portion and the second portion, and in a plan view, the gap extends along a portion of an edge of the second opening.
5. 5 . The display panel of claim 4 , wherein the second portion includes a contact portion electrically connected to the second pixel circuit, and the connection electrode connects the first pixel electrode and the second portion to each other.
6. 6 . The display panel of claim 4 , wherein the second pixel electrode and the third pixel electrode are adjacent to each other in a first direction, and the second pixel electrode includes a protrusion protruding in a second direction intersecting the first direction.
7. 7 . The display panel of claim 6 , wherein the second portion includes the protrusion.
8. 8 . The display panel of claim 1 , wherein each of the first pixel circuit, the second pixel circuit, and the third pixel circuit comprises: a first transistor including a gate, a first terminal, and a second terminal, the gate being connected to a first node, the first terminal being connected to a driving voltage line, and the second terminal being connected to a second node; a second transistor connected between the first node and one of a first data line, a second data line, and a third data line; a third transistor connected between an initialization-sensing line and the second node; and a capacitor connected between the first node and the second node.
9. 9 . The display panel of claim 8 , wherein the second transistor of the first pixel circuit is connected to the first data line, the second node of the first pixel circuit is connected to the first pixel electrode, the second transistor of the second pixel circuit is connected to the second data line, the second node of the second pixel circuit is connected to the second pixel electrode, the third transistor of the third pixel circuit is connected to the third data line, and the second node of the third pixel circuit is connected to the third pixel electrode.
10. 10 . The display panel of claim 8 , wherein the second transistor of the second pixel circuit is connected to the first data line, and the second node of the second pixel circuit is connected to the first pixel electrode.
11. 11 . A display panel comprising: a pixel circuit set including a first pixel circuit, a second pixel circuit, and a third pixel circuit; a first pixel electrode overlapping the first pixel circuit in a plan view; a second pixel electrode overlapping the second pixel circuit in a plan view; a third pixel electrode overlapping the third pixel circuit in a plan view; and a connection electrode that connects the first pixel electrode and the second pixel electrode to each other, wherein the second pixel electrode includes a first portion and a second portion, the second portion being spaced apart from the first portion with a gap between the first portion and the second portion and connected to the connection electrode.
12. 12 . The display panel of claim 11 , further comprising: a bank layer arranged over the first pixel electrode, the second pixel electrode, and the third pixel electrode, the bank layer including a first opening overlapping the first pixel electrode, a second opening overlapping the second pixel electrode, and a third opening overlapping the third pixel electrode in a plan view.
13. 13 . The display panel of claim 12 , wherein the first opening is larger than the second opening and the third opening in a plan view, and the second opening is smaller than the third opening in a plan view.
14. 14 . The display panel of claim 12 , wherein, in a plan view, the gap extends along a portion of an edge of the second opening.
15. 15 . The display panel of claim 11 , wherein the second portion includes a contact portion electrically connected to the second pixel circuit, and the connection electrode connects the first pixel electrode and the second portion to each other.
16. 16 . The display panel of claim 11 , wherein the second pixel electrode and the third pixel electrode are adjacent to each other in a first direction, and the second pixel electrode includes a protrusion protruding in a second direction intersecting the first direction.
17. 17 . The display panel of claim 16 , wherein the first portion includes the protrusion.
18. 18 . The display panel of claim 16 , wherein the second portion includes the protrusion.
19. 19 . An electronic apparatus comprising: a display panel; and a processor that drives the display panel, wherein the display panel comprises: a pixel circuit set including a first pixel circuit, a second pixel circuit, and a third pixel circuit; a first pixel electrode overlapping the first pixel circuit in a plan view; a second pixel electrode overlapping the second pixel circuit in a plan view; a third pixel electrode overlapping the third pixel circuit in a plan view; and a connection electrode that connects the first pixel electrode and the second pixel electrode to each other, and the second pixel electrode includes a first portion and a second portion, the second portion being spaced apart from the first portion with a gap between the first portion and the second portion and connected to the connection electrode.
20. 20 . The electronic apparatus of claim 19 , wherein the connection electrode is arranged below the first pixel electrode, the second pixel electrode, and the third pixel electrode, and in a plan view, an end of the connection electrode overlaps the first portion of the first pixel electrode, and another end of the connection electrode overlaps the second pixel electrode.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application claims priority to and the benefits of Korean Patent Application No. 10-2024-0153717 under 35 U.S.C. § 119, filed on Nov. 1, 2024, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. BACKGROUND 1. Technical Field Embodiments relate to a display panel and an electronic apparatus including the same. 2. Description of the Related Art A display panel may include multiple pixels. Each pixel may include subpixels that emit light of different colors. Each of the subpixels may include a light-emitting element including an emission layer, and a pixel circuit configured to control the luminance of the light-emitting element. The pixel circuit may include thin-film transistors, capacitors, and lines. Recently, display panels have become thinner and lighter and thus may be applied to various electronic apparatuses. Because the display panels as described above are widely used, various forms of display panels and electronic apparatuses including the same have been designed. SUMMARY Defects in some of pixel circuits may cause bright spots or dark spots to appear on a display panel. In this regard, embodiments include a display panel that displays high-quality images by using a repair process of connecting, to a normal pixel circuit, light-emitting diodes connected to a defective pixel circuit, and an electronic apparatus including the display panel. However, the scope of the disclosure is not limited thereto. Additional aspects will be set forth in part in the description that follows and, in part, will be apparent from the description, or may be learned by practice of the embodiments of the disclosure. According to an embodiment, a display panel may include a pixel circuit set including a first pixel circuit, a second pixel circuit, and a third pixel circuit, a first pixel electrode overlapping the first pixel circuit in a plan view, a second pixel electrode overlapping the second pixel circuit in a plan view, a third pixel electrode overlapping the third pixel circuit in a plan view, and a connection electrode arranged below the first pixel electrode, the second pixel electrode, and the third pixel electrode. In a plan view, an end of the connection electrode may overlap the first pixel electrode, and another end of the connection electrode may overlap the second pixel electrode. In an embodiment, the display panel may further include a bank layer arranged over the first pixel electrode, the second pixel electrode, and the third pixel electrode, the bank layer including a first opening overlapping the first pixel electrode, a second opening overlapping the second pixel electrode, and a third opening overlapping the third pixel electrode in a plan view. In an embodiment, the first opening may be larger than the second opening and the third opening in a plan view, and the second opening may be smaller than the third opening in a plan view. In an embodiment, the second pixel electrode may include a first portion and a second portion, the first portion overlapping the second opening in a plan view, and the second portion being spaced apart from the first portion with a gap between the first portion and the second portion, and in a plan view, the gap may extend along a portion of an edge of the second opening. In an embodiment, the second portion may include a contact portion electrically connected to the second pixel circuit, and the connection electrode may connect the first pixel electrode and the second portion to each other. In an embodiment, the second pixel electrode and the third pixel electrode may be adjacent to each other in a first direction, and the second pixel electrode may include a protrusion protruding in a second direction intersecting the first direction. In an embodiment, the second portion may include the protrusion. In an embodiment, each of the first pixel circuit, the second pixel circuit, and the third pixel circuit may include a first transistor including a gate, a first terminal, and a second terminal, the gate being connected to a first node, the first terminal being connected to a driving voltage line, and the second terminal being connected to a second node, a second transistor connected between the first node and one of a first data line, a second data line, and a third data line, a third transistor connected between an initialization-sensing line and the second node, and a capacitor connected between the first node and the second node. In an embodiment, the second transistor of the first pixel circuit may be connected to the first data line, the second node of the first pixel circuit may be connected to the first pixel electrode, the second transistor of the second pixel circuit may be connected to the second data line, the second node of the second pixel circuit may be connected to the second pixel electrode, the third transistor of the third pixel circuit may be conn