US-20260130115-A1 - METHOD OF FABRICATING A MAGNETORESISTIVE BIT FROM A MAGNETORESISTIVE STACK

Abstract

A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes (a) etching through at least a portion of a thickness of the surface region to create a first set of exposed areas in the form of multiple strips extending in a first direction, and (b) etching through at least a portion of a thickness of the surface region to create a second set of exposed areas in the form of multiple strips extending in a second direction. The first set of exposed areas and the second set of exposed areas may have multiple areas that overlap. The method may also include, (c) after the etching in (a) and (b), etching through at least a portion of the thickness of the magnetoresistive stack through the first set and second set of exposed areas.

Inventors

• Kerry Joseph Nagel
• Sanjeev Aggarwal
• Sarin A. Deshpande

Assignees

• EVERSPIN TECHNOLOGIES, INC.

Dates

Publication Date

20260507

Application Date

20251222

Claims (20)

1. 1 . A method of fabricating a magnetoresistive bit, the method comprising: etching through at least a portion of a hardmask region with a first etch; etching through at least a portion of an interfacing region with a second etch after the first etch to expose a first layer; exposing the first layer to gases of (i) silicon and oxygen gases or (ii) silicon and nitrogen gases immediately after the second etch; etching through at least a portion of a first intermediate region with a third etch after the second etch to expose a second layer; exposing the second layer to gases of (i) silicon and oxygen gases or (ii) silicon and nitrogen gases immediately after the third etch; etching through at least a portion of a second intermediate region with a fourth etch after the third etch to expose a third layer; and exposing the third layer to gases of (i) silicon and oxygen gases or (ii) silicon and nitrogen gases immediately after the fourth etch.
2. 2 . The method of claim 1 , wherein exposing the first layer to gases of (i) silicon and oxygen gases or (ii) silicon and nitrogen gases includes depositing a first encapsulant on the first layer after the second etch.
3. 3 . The method of claim 1 , wherein exposing the second layer to gases of (i) silicon and oxygen gases or (ii) silicon and nitrogen gases includes depositing a second encapsulant on the second layer after the third etch.
4. 4 . The method of claim 1 , wherein exposing the third layer to gases of (i) silicon and oxygen gases or (ii) silicon and nitrogen gases includes depositing a third encapsulant on the third layer after the fourth etch.
5. 5 . The method of claim 1 , wherein the first layer includes multiple substantially parallel strips that extend in a first direction, and the second layer includes multiple substantially parallel strips that extend in a second direction different from the first direction.
6. 6 . The method of claim 1 , wherein the first layer includes multiple strips arranged substantially parallel to and spaced substantially equidistant from each other.
7. 7 . The method of claim 1 , wherein the first intermediate region includes multiple stacked layers.
8. 8 . The method of claim 1 , wherein the second intermediate region includes multiple stacked layers.
9. 9 . The method of claim 1 , wherein the first etch is an etching process utilizing a chemical reagent, and the third etch is a physical etching process.
10. 10 . The method of claim 1 , wherein the first etch and the second etch are etching processes utilizing a chemical reagent.
11. 11 . The method of claim 1 , wherein the third etch uses ion beam etching.
12. 12 . A method of fabricating a magnetoresistive bit from a magnetoresistive stack including at least two magnetic regions, a hardmask region, an interfacing region, a first intermediate region, and a second intermediate region, the first and second intermediate regions positioned between the two magnetic regions, the method comprising: etching through the hardmask region with a first etch; exposing a first layer in the interfacing region with a second etch after the first etch; exposing the first layer to gases of (i) silicon and oxygen gases or (ii) silicon and nitrogen gases immediately after the second etch; exposing a second layer in the first intermediate region with a third etch after the second etch; exposing the second layer to gases of (i) silicon and oxygen gases or (ii) silicon and nitrogen gases immediately after the third etch; exposing a third layer in the second intermediate region with a fourth etch after the third etch; and exposing the third layer to gases of (i) silicon and oxygen gases or (ii) silicon and nitrogen gases immediately after the fourth etch.
13. 13 . The method of claim 12 , wherein exposing the first layer to gases of (i) silicon and oxygen gases or (ii) silicon and nitrogen gases includes depositing a first encapsulant on the first layer after the second etch.
14. 14 . The method of claim 12 , wherein exposing the second layer to gases of (i) silicon and oxygen gases or (ii) silicon and nitrogen gases includes depositing a second encapsulant on the second layer after the third etch.
15. 15 . The method of claim 12 , wherein exposing the third layer to gases of (i) silicon and oxygen gases or (ii) silicon and nitrogen gases includes depositing a third encapsulant on the third layer after the fourth etch.
16. 16 . The method of claim 12 , wherein the first etch is an etching process utilizing a chemical reagent, wherein the third etch is a physical etching process.
17. 17 . The method of claim 12 , wherein the first etch and the second etch are etching processes utilizing a chemical reagent.
18. 18 . The method of claim 12 , wherein the third etch uses ion beam etching.
19. 19 . A method of fabricating a magnetoresistive bit from a magnetoresistive stack including at least two magnetic regions, a hardmask region, an interfacing region, a first intermediate region, and a second intermediate region, the first and second intermediate regions positioned between the two magnetic regions, the method comprising: (a) etching through at least a portion of the hardmask region with a first etch; (b) etching through at least a portion of the interfacing region with a second etch after the first etch; (c) etching through a least a portion of the first intermediate region with a third etch after the second etch; (d) etching through a least a portion of the second intermediate region with a fourth etch after the third etch; and (e) immediately after the etching in (b), (c), and (d), contacting exposed layers with (i) silicon and oxygen gases or (ii) silicon and nitrogen gases.
20. 20 . The method of claim 19 , wherein contacting the exposed layers with (i) silicon and oxygen gases or (ii) silicon and nitrogen gases comprises depositing an encapsulant on each layer after the etching in (b), (c), and (d).

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 18/484,202, filed Oct. 10, 2023, which is a continuation of U.S. patent application Ser. No. 17/109,318, filed Dec. 2, 2020, which is a continuation of U.S. patent application Ser. No. 16/881,151, filed May 22, 2020 (now U.S. Pat. No. 10,886,463), which is a continuation of U.S. patent application Ser. No. 16/108,762, filed Aug. 22, 2018 (now U.S. Pat. No. 10,700,268), which claims the benefit of U.S. Provisional Application No. 62/551,400, filed Aug. 29, 2017, the entireties of which are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to, among other things, embodiments and aspects related to manufacturing integrated circuit devices and the devices resulting therefrom. INTRODUCTION There are many inventions described and illustrated herein, as well as many aspects and embodiments of those inventions. In one aspect, the present disclosure relates to methods of manufacturing an integrated circuit device and the devices resulting therefrom. To describe aspects of the disclosed method, an exemplary method of manufacturing a magnetoresistive device (for example, a magnetoresistive memory, a magnetoresistive sensor/transducer, etc.) from a magnetoresistive stack/structure is described herein. However, this is only exemplary, and the disclosed method can be applied to manufacture any integrated circuit device. BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the present disclosure may be implemented in connection with aspects illustrated in the attached drawings. These drawings show different aspects of the present disclosure and, where appropriate, reference numerals illustrating like structures, components, materials and/or elements in different figures are labeled similarly. It is understood that various combinations of the structures, components, and/or elements, other than those specifically shown, are contemplated and are within the scope of the present disclosure. For simplicity and clarity of illustration, the figures depict the general structure and/or manner of construction of the various embodiments. For ease of illustration, the figures depict the different regions along the thickness of the illustrated magnetoresistive stacks as a layer having well defined boundaries (i.e., depicted using lines). However, one skilled in the art would understand that, in reality, at an interface between adjacent regions or layers, the materials of these regions may alloy together, or migrate into one or the other material, and make their boundaries ill-defined or diffuse. That is, although multiple layers with distinct interfaces are illustrated in the figures, in some cases, over time and/or exposure to high temperatures, materials of some of the layers may migrate into or interact with materials of other layers to present a more diffuse interface between these layers. Further, although the figures illustrate each region or layer as having a relatively uniform thickness across its width, a skilled artisan would recognize that, in reality, the different regions may have a non-uniform thickness (e.g., the thickness of a layer may vary along the width of the layer). In the figures and description, details of well-known features (e.g., interconnects, etc.) and manufacturing techniques (e.g., deposition techniques, etching techniques, etc.) may be omitted for the sake of brevity (and to avoid obscuring other features), since these features/technique are well known to a skilled artisan. Elements in the figures are not necessarily drawn to scale. The dimensions of some features may be exaggerated relative to other features to improve understanding of the exemplary embodiments. Cross-sectional views are simplifications provided to help illustrate the relative positioning of various regions/layers and to describe various processing steps. One skilled in the art would appreciate that the cross-sectional views are not drawn to scale and should not be viewed as representing dimensional relationships between different regions/layers. Moreover, while certain regions/layers and features are illustrated with straight 90-degree edges, in reality, such regions/layers may be more “rounded” and/or gradually sloping. It should also be noted that, even if it is not specifically mentioned, aspects described with reference to one embodiment may also be applicable to, and may be used with, other embodiments. FIG. 1 is a cross-sectional schematic illustration of the structure of an exemplary magnetoresistive stack/structure (magnetoresistive stack) used to form a magnetoresistive device, according to principles of the current disclosure; FIG. 2 is a cross-sectional schematic illustrating a mask deposited on the magnetoresistive stack of FIG. 1 during processing of the magnetoresistive stack to form a magnetoresistive device; FIG. 3 is a cross-sectional schematic illustration of the magnetoresistive st