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US-20260130116-A1 - METHOD FOR FORMING A HARD MASK WITH A TAPERED PROFILE

US20260130116A1US 20260130116 A1US20260130116 A1US 20260130116A1US-20260130116-A1

Abstract

Various embodiments of the present disclosure are directed towards a method for forming a memory cell. In some embodiments, a memory film is deposited over a substrate and comprises a bottom electrode layer, a top electrode layer, and a data storage film between the top and bottom electrode layers. A hard mask film is deposited over the memory film and comprises a conductive hard mask layer. The top electrode layer and the hard mask film are patterned to respectively form a top electrode and a hard mask over the top electrode. A trimming process is performed to decrease a sidewall angle between a sidewall of the hard mask and a bottom surface of the hard mask. An etch is performed into the data storage film with the hard mask in place after the trimming process to form a data storage structure underlying the top electrode.

Inventors

  • Min-Yung KO
  • Chern-Yow Hsu
  • Chang-Ming Wu
  • Shih-Chang Liu

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date
20260507
Application Date
20260102

Claims (20)

  1. 1 . A semiconductor device structure, comprising: an interconnect structure over a substrate and comprising an alternating stack of wires and vias; a cell structure comprising: a bottom electrode overlying a lower portion of the interconnect structure; a dielectric layer overlying the bottom electrode; and a top electrode overlying the dielectric layer and underlying an upper portion of the interconnect structure, wherein a sidewall of the top electrode is oriented at an angle of less than about 82 degrees relative to a bottom surface of the top electrode, and wherein the angle faces an interior of the top electrode in a cross-sectional plane; and a sidewall spacer on the sidewall of the top electrode and a sidewall of the dielectric layer.
  2. 2 . The semiconductor device structure according to claim 1 , wherein the angle is greater than about 75 degrees.
  3. 3 . The semiconductor device structure according to claim 1 , wherein the interconnect structure comprises a wire overlying the top electrode and further comprises a via extending from the wire to the top electrode, and wherein the via is spaced from the sidewall of the top electrode.
  4. 4 . The semiconductor device structure according to claim 1 , wherein a sidewall of the bottom electrode, the sidewall of the dielectric layer, and the sidewall of the top electrode form a common sidewall on which the sidewall spacer is arranged.
  5. 5 . The semiconductor device structure according to claim 1 , further comprising: a hard mask overlying the top electrode, wherein the hard mask comprises a metal element.
  6. 6 . The semiconductor device structure according to claim 1 , wherein the sidewall spacer overlies the bottom electrode.
  7. 7 . The semiconductor device structure according to claim 1 , wherein the cell structure increases in width from a top of the top electrode to a bottom of the bottom electrode.
  8. 8 . A semiconductor device structure, comprising: an interconnect structure over a substrate and comprising an alternating stack of wires and vias; and a cell structure comprising: a bottom electrode overlying a lower portion of the interconnect structure; a dielectric layer overlying the bottom electrode; and a top electrode overlying the dielectric layer and underlying an upper portion of the interconnect structure, wherein the top electrode has a first concentration of ions at a sidewall of the top electrode, and wherein the first concentration is higher than a second concentration of the ions that the dielectric layer has at a sidewall of the dielectric layer that neighbors the sidewall of the top electrode.
  9. 9 . The semiconductor device structure according to claim 8 , wherein the first concentration is higher than a third concentration of the ions that the top electrode has at a width-wise center of the top electrode.
  10. 10 . The semiconductor device structure according to claim 9 , wherein the top electrode has a ring-shaped region at the sidewall of the top electrode, and wherein the ring-shaped region has the first concentration of the ions and surrounds the width-wise center.
  11. 11 . The semiconductor device structure according to claim 8 , wherein the ions comprise at least one of helium, argon, krypton, or xenon.
  12. 12 . The semiconductor device structure according to claim 8 , wherein the ions comprise a plurality of different elements.
  13. 13 . The semiconductor device structure according to claim 8 , wherein the dielectric layer comprises a metal oxide.
  14. 14 . The semiconductor device structure according to claim 8 , wherein the cell structure further comprises: a pair of ferromagnetic layers between the bottom electrode and the top electrode, wherein the dielectric layer is between the pair of ferromagnetic layers.
  15. 15 . A semiconductor device structure, comprising: a bottom electrode overlying a substrate; a dielectric layer overlying the bottom electrode; a top electrode overlying the dielectric layer; and a hard mask overlying the top electrode; wherein a sidewall of the top electrode is oriented at an angle of about 75-82 degrees relative to a bottom surface of the top electrode, and wherein the angle faces an interior of the top electrode in a cross-sectional plane.
  16. 16 . The semiconductor device structure according to claim 15 , wherein the hard mask comprises dielectric material and metal.
  17. 17 . The semiconductor device structure according to claim 15 , further comprising: a conductive wire overlying the top electrode; and a conductive via extending from the conductive wire, through the hard mask, to the top electrode.
  18. 18 . The semiconductor device structure according to claim 17 , wherein a thickness of the hard mask decreases from the conductive via to the sidewall of the top electrode.
  19. 19 . The semiconductor device structure according to claim 15 , further comprising: a magnetic tunnel junction (MTJ) between the top electrode and the bottom electrode, wherein the MTJ comprises the dielectric layer.
  20. 20 . The semiconductor device structure according to claim 15 , wherein the bottom electrode, the dielectric layer, and the top electrode form a resistive random-access memory (RRAM) memory cell.

Description

REFERENCE TO RELATED APPLICATIONS This Application is a Continuation of U.S. application Ser. No. 18/772,350, filed on Jul. 15, 2024, which is a Continuation of U.S. application Ser. No. 18/353,254, filed on Jul. 17, 2023 (now U.S. Pat. No. 12,114,576, issued on Oct. 8, 2024), which is a Divisional of U.S. application Ser. No. 17/078,630, filed on Oct. 23, 2020 (now U.S. Pat. No. 11,765,980, issued on Sep. 19, 2023), which claims the benefit of U.S. Provisional Application No. 63/072,343, filed on Aug. 31, 2020. The contents of the above-referenced Patent Applications are hereby incorporated by reference in their entirety. BACKGROUND Many modern-day electronic devices include electronic memory. Electronic memory may be volatile memory or non-volatile memory. Non-volatile memory is able to store data in the absence of power, whereas volatile memory is not. Magnetoresistive random-access memory (MRAM) and resistive random-access memory (RRAM) are promising candidates for next generation non-volatile memory due to relatively simple structures and compatibility with complementary metal-oxide-semiconductor (CMOS) manufacturing processes. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1-4 illustrate a series of cross-sectional views of some embodiments of a method for forming and using a hard mask with a tapered profile. FIG. 5 illustrates a graph of some embodiments of a curve describing sputter yield as a function of ion angle during ion bombardment of FIG. 3. FIG. 6 illustrates a block diagram of some embodiments of the method of FIGS. 1-4. FIG. 7 illustrates a cross-sectional view of some embodiments of an integrated circuit (IC) comprising a memory cell formed using the method of FIGS. 1-4. FIG. 8 illustrates a top view of some embodiments of the memory cell of FIG. 7. FIG. 9 illustrates a cross-sectional view of some alternative embodiments of the IC of FIG. 7 in which a sidewall spacer is on a sidewall of a bottom electrode. FIG. 10 illustrates a cross-sectional view of some alternative embodiments of the IC of FIG. 7 in which the memory cell comprises a magnetic tunnel junction (MTJ). FIG. 11 illustrates a cross-sectional view of some embodiments of an IC comprising a plurality of memory cells formed using the method of FIGS. 1-4. FIGS. 12-20 illustrate a series of cross-sectional views of some embodiments of a method for forming an IC comprising a plurality of memory cells in which the memory cells are formed using hard masks with tapered profiles. FIG. 21 illustrates a block diagram of some embodiments of the method of FIGS. 12-20. FIGS. 22-25 illustrate a series of cross-sectional views of some alternative embodiments of the method of FIGS. 12-20 in which a second etch extends into a bottom electrode layer. FIG. 26 illustrates a block diagram of some embodiments of the method of FIGS. 22-25. FIGS. 27 and 28 illustrate cross-sectional views of some alternative embodiments of the structures respectively in FIGS. 16 and 17. DETAILED DESCRIPTION The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. A magnetoresistive random-access memory (MRAM) cell may com