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US-20260130117-A1 - TECHNIQUES FOR MRAM MTJ TOP ELECTRODE CONNECTION

US20260130117A1US 20260130117 A1US20260130117 A1US 20260130117A1US-20260130117-A1

Abstract

Some embodiments relate to an integrated chip having a memory cell over a substrate. The memory cell includes a first electrode. An electrode contact is on an upper surface of the first electrode. A width of an upper surface of the electrode contact is greater than a width of the upper surface of the first electrode and a thickness of the electrode contact. A first conductive interconnect structure contacts the upper surface of the electrode contact. A width of the first conductive interconnect structure is greater than the width of the upper surface of the electrode contact. A second conductive interconnect structure overlies the first conductive interconnect structure. Thicknesses of the first and second conductive interconnect structures are greater than the thickness of the electrode contact.

Inventors

  • Harry-Hak-Lay Chuang
  • Chen-Pin Hsu
  • Hung Cho Wang
  • Wen-Chun YOU
  • Sheng-Chang Chen
  • Tsun Chung Tu
  • Jiunyu Tsai
  • Sheng-Huang Huang

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date
20260507
Application Date
20260102

Claims (20)

  1. 1 . An integrated chip, comprising: a memory cell over a substrate and comprising a first electrode; an electrode contact contacting an upper surface of the first electrode, wherein a width of an upper surface of the electrode contact is greater than a width of the upper surface of the first electrode and a thickness of the electrode contact; a first conductive interconnect structure contacting the upper surface of the electrode contact, wherein a width of the first conductive interconnect structure is greater than the width of the upper surface of the electrode contact; and a second conductive interconnect structure over and contacting the first conductive interconnect structure, wherein thicknesses of the first and second conductive interconnect structures are greater than the thickness of the electrode contact.
  2. 2 . The integrated chip of claim 1 , wherein a first sidewall of the electrode contact adjacent to a first sidewall of the first electrode has a height greater than a height of the first sidewall of the first electrode.
  3. 3 . The integrated chip of claim 2 , wherein a bottom of the first sidewall of the electrode contact contacts a top of the first sidewall of the first electrode.
  4. 4 . The integrated chip of claim 2 , wherein a second sidewall of the electrode contact opposite the first sidewall of the electrode contact has a height less than the height of the first sidewall of the electrode contact.
  5. 5 . The integrated chip of claim 1 , wherein a width of the second conductive interconnect structure is greater than the thickness of the electrode contact.
  6. 6 . The integrated chip of claim 1 , further comprising: a first dielectric layer around the memory cell and the electrode contact, wherein an upper surface of the first dielectric layer is substantially aligned with the upper surface of the electrode contact; and an etch stop layer on the first dielectric layer and around the first conductive interconnect structure.
  7. 7 . The integrated chip of claim 6 , wherein the first conductive interconnect structure comprises a vertical segment extending below a bottom surface of the etch stop layer and contacting a first sidewall of the electrode contact, wherein a height of the vertical segment is less than the thickness of the electrode contact.
  8. 8 . The integrated chip of claim 1 , wherein the memory cell comprises a second electrode and a data storage structure between the second electrode and the first electrode, wherein a thickness of the second electrode is less than the thickness of the electrode contact, wherein a width of the second electrode is greater than the width of the upper surface of the electrode contact.
  9. 9 . An integrated chip, comprising: a memory cell comprising a first electrode having a first sidewall and a second sidewall opposite the first sidewall; an electrode contact on the first electrode, wherein a first outer sidewall of the electrode contact overhangs the first sidewall of the first electrode, wherein a second outer sidewall of the electrode contact is laterally offset from an outer edge of the second sidewall of the first electrode in a direction towards the first outer sidewall, wherein a bottom of the first outer sidewall is below a bottom of the second outer sidewall; and a first conductive interconnect structure on the electrode contact.
  10. 10 . The integrated chip of claim 9 , wherein a first vertical distance between a top surface of the electrode contact and the bottom of the second outer sidewall is less than a height of the second sidewall of the first electrode.
  11. 11 . The integrated chip of claim 10 , wherein a second vertical distance between the bottom of the first outer sidewall and the bottom of the second outer sidewall is less than the first vertical distance.
  12. 12 . The integrated chip of claim 9 , wherein the bottoms of the first and second outer sidewalls physically contact the first electrode.
  13. 13 . The integrated chip of claim 9 , wherein a width of the first conductive interconnect structure is greater than a width of a bottom surface of the electrode contact, and a height of the first conductive interconnect structure is greater than a height of the electrode contact.
  14. 14 . The integrated chip of claim 9 , further comprising: a sidewall spacer on the first and second sidewalls of the first electrode, wherein the sidewall spacer comprises a single continuous layer extending from the first sidewall of the first electrode to the bottom of the first outer sidewall.
  15. 15 . The integrated chip of claim 9 , wherein the memory cell comprises a second electrode and a data storage structure between the second electrode and the first electrode, wherein the first and second outer sidewalls are spaced between outer opposing sidewalls of the second electrode.
  16. 16 . An integrated chip, comprising: a first dielectric layer over a substrate; a memory cell in the first dielectric layer and comprising an electrode; a conductive structure in the first dielectric layer and on the electrode, wherein a top surface of the conductive structure is aligned with a top surface of the first dielectric layer; a first conductive interconnect structure on the conductive structure; a second dielectric layer over the substrate and adjacent to the first dielectric layer; a second conductive interconnect structure in the second dielectric layer and having a top surface below a top surface of the second dielectric layer; and a third conductive interconnect structure in the second dielectric layer and on the second conductive interconnect structure, wherein a top surface of the third conductive interconnect structure is aligned with the top surface of the conductive structure, wherein a width of the third conductive interconnect structure is greater than a height of the conductive structure.
  17. 17 . The integrated chip of claim 16 , further comprising: an etch stop layer over the first and second dielectric layers, wherein a vertical distance between a bottom surface of the etch stop layer and a top surface of the electrode is less than a height of the electrode.
  18. 18 . The integrated chip of claim 16 , wherein heights of the second and third conductive interconnect structures are greater than the height of the conductive structure.
  19. 19 . The integrated chip of claim 16 , wherein the first dielectric layer is a continuous uniform layer extending around the electrode and the conductive structure, wherein the first dielectric layer is laterally offset from the second and third conductive interconnect structures.
  20. 20 . The integrated chip of claim 19 , wherein a dielectric constant of the first dielectric layer is different from a dielectric constant of the second dielectric layer.

Description

REFERENCE TO RELATED APPLICATIONS This Application is a Continuation of U.S. application Ser. No. 17/725,842, filed on Apr. 21, 2022, which is a Continuation of U.S. application Ser. No. 17/381,635, filed on Jul. 21, 2021 (now U.S. Pat. No. 12,426,514, issued on Sep. 23, 2025), which is a Continuation of U.S. application Ser. No. 16/408,815, filed on May 10, 2019 (now U.S. Pat. No. 11,075,335, issued on Jul. 27, 2021), which claims the benefit of U.S. Provisional Application No. 62/736,607, filed on Sep. 26, 2018. The contents of the above-referenced Patent Applications are hereby incorporated by reference in their entirety. BACKGROUND Many modern day electronic devices contain electronic memory. Electronic memory may be volatile memory or non-volatile memory. Non-volatile memory is able to retain its stored data in the absence of power, whereas volatile memory loses its stored data when power is lost. Magnetoresistive random-access memory (MRAM) is one promising candidate for next generation non-volatile electronic memory due to advantages over current electronic memory. Compared to current non-volatile memory, such as flash random-access memory, MRAM typically is faster and has better endurance. Compared to current volatile memory, such as dynamic random-access memory (DRAM) and static random-access memory (SRAM), MRAM typically has similar performance and density, but lower power consumption. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates a cross-sectional view of some embodiments of a memory device including a MRAM cell having a magnetic tunneling junction (MTJ), according to the present disclosure. FIGS. 2A-2B illustrate cross-sectional views of some embodiments of an integrated chip including an embedded memory region comprising a MRAM cell having a magnetic tunneling junction (MTJ) and a logic region, according to the present disclosure. FIGS. 3-14 illustrate cross-sectional views of some embodiments of a method of forming a memory device including an embedded memory region comprising a MRAM cell having a MTJ and a logic region, according to the present disclosure. FIG. 15 illustrates a methodology in flowchart format that illustrates some embodiments of a method of forming a memory device including an embedded memory region comprising a MRAM cell having a MTJ and a logic region, according to the present disclosure. DETAILED DESCRIPTION The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. MRAM cells are generally located within an ILD structure surrounding stacked interconnect layers over a substrate. A magnetoresistive random-access memory (MRAM) cell generally includes a magnetic tunnel junction (MTJ) arranged between top and bottom electrodes. The bottom electrode is coupled to the stacked interconnect layers by a bottom electrode via while the top electrode is coupled to the stacked interconnect layers by a top electrode via. In conventional MRAM cell fabrication, the top electrode via is formed by etching an inter-level dielectric (ILD) arranged over the top electrode to form an opening over the top electrode. The opening is subsequ