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US-20260130121-A1 - MAGNETIC TUNNELING JUNCTION WITH SYNTHETIC FREE LAYER FOR SOT-MRAM

US20260130121A1US 20260130121 A1US20260130121 A1US 20260130121A1US-20260130121-A1

Abstract

A magnetic memory device includes a spin-orbit torque (SOT) induction spin Hall electrode and a free layer of a magnetic tunnel junction (MTJ) stack disposed on the spin Hall electrode which is a synthetic anti-ferromagnetic structure. The free layer has a magnetic moment which is askew of the long axis of the MTJ stack and askew the direction of current flow through the spin Hall electrode. The MTJ stack internally generates a magnetic field to switch the state of the free layer. The free layer includes a first layer separated from a second layer by a spacer layer, where the first layer and the second layer may have the same or different crystalline structures.

Inventors

  • Chien-Min Lee
  • Shy-Jay Lin

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date
20260507
Application Date
20251230

Claims (20)

  1. 1 . A method for fabricating a semiconductor device, comprising: forming a spin orbit torque (SOT) layer on a substrate; forming a magnetic tunneling junction (MTJ) on the SOT layer; forming a first cap layer on the MTJ; forming a first inter-metal dielectric (IMD) layer on the first cap layer; and forming a second cap layer on the first cap layer and the first IMD layer.
  2. 2 . The method of claim 1 , further comprising: forming a second IMD layer on the first cap layer, the first IMD layer, and the second cap layer; and planarizing the first cap layer, the first IMD layer, the second cap layer, and the second IMD layer.
  3. 3 . The method of claim 1 , further comprising: performing a first etching process to pattern the first IMD layer; and performing a second etching process to pattern the first cap layer and the first IMD layer.
  4. 4 . The method of claim 3 , further comprising patterning the first IMD layer to expose a top surface of the first cap layer.
  5. 5 . The method of claim 3 , further comprising performing the second etching process so that top surfaces of the first cap layer and the first IMD layer are coplanar.
  6. 6 . The method of claim 1 , further comprising forming the second cap layer on a sidewall of the SOT layer.
  7. 7 . The method of claim 1 , further comprising forming the second cap layer on a sidewall of the first cap layer.
  8. 8 . The method of claim 1 , further comprising forming the second cap layer on a sidewall of the first IMD layer.
  9. 9 . The method of claim 1 , wherein the first cap layer and the second cap layer comprise a same material.
  10. 10 . The method of claim 1 , wherein the first cap layer and the second cap layer are formed in a same process.
  11. 11 . A semiconductor device comprising: a spin Hall electrode over a substrate; a magnetic tunneling junction (MTJ) on the spin Hall electrode, the MTJ comprising a synthetic free layer on the spin Hall electrode, a barrier layer on the synthetic free layer, and a reference layer structure on the barrier layer; a capping layer on the MTJ; a conformal insulating layer encapsulating the MTJ and extending over the spin Hall electrode; and an inter-layer dielectric surrounding the spin Hall electrode and the MTJ.
  12. 12 . The semiconductor device of claim 11 , wherein the synthetic free layer comprises a first magnetic layer, a second magnetic layer, and a spacer layer interposed between the first magnetic layer and the second magnetic layer.
  13. 13 . The semiconductor device of claim 12 , wherein the first magnetic layer and the second magnetic layer are antiferromagnetically coupled through the spacer layer.
  14. 14 . The semiconductor device of claim 11 , wherein the spin Hall electrode comprises platinum, palladium, gold, tantalum, tungsten, or combinations thereof.
  15. 15 . The semiconductor device of claim 11 , further comprising a top electrode on the capping layer, wherein the conformal insulating layer extends along a sidewall of the top electrode.
  16. 16 . A semiconductor device, comprising: a spin orbit torque (SOT) layer on a substrate; a magnetic tunneling junction (MTJ) on the SOT layer, wherein the MTJ comprises a circular shape in a top view; and a first cap layer around the MTJ, wherein the first cap layer comprises a first ring in a top view.
  17. 17 . The semiconductor device of claim 16 , further comprising a first inter-metal dielectric (IMD) layer around the first cap layer, wherein the first IMD layer comprises a second ring in a top view.
  18. 18 . The semiconductor device of claim 17 , further comprising a second cap layer around the first IMD layer, wherein the second cap layer comprises a third ring in a top view.
  19. 19 . The semiconductor device of claim 18 , further comprising a second IMD layer around the second cap layer.
  20. 20 . The semiconductor device of claim 16 , wherein the MTJ comprises an ellipse in a top view.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This application is a continuation of U.S. patent application Ser. No. 18/912,177, filed on Oct. 10, 2024, which is a continuation of U.S. patent application Ser. No. 18/447,912, filed on Aug. 10, 2023, now U.S. Pat. No. 12,329,041 issued on Jun. 10, 2025, which is a divisional of U.S. patent application Ser. No. 17/145,048, filed on Jan. 8, 2021, now U.S. Pat. No. 11,844,287 issued on Dec. 12, 2023, which application claims priority to U.S. Provisional Application No. 63/027,643, filed on May 20, 2020, which applications are hereby incorporated by reference herein as if reproduced entirely herein. BACKGROUND A magnetic random access memory (MRAM) offers comparable performance to volatile static random access memory (SRAM) and comparable density with lower power consumption to volatile dynamic random access memory (DRAM). Compared to non-volatile memory (NVM) flash memory, an MRAM offers much faster access times and suffers minimal degradation over time, whereas a flash memory can only be rewritten a limited number of times. One type of an MRAM is a spin transfer torque magnetic random access memory (STT-MRAM). An STT-MRAM utilizes a magnetic tunneling junction (MTJ) written at least in part by a current driven through the MTJ. Another type of an MRAM is a spin orbit torque (SOT) MRAM (SOT-MRAM), which generally requires a lower switching current than an STT-MRAM. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying Figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1 through 3 are schematic views of an SOT-MRAM cell according to some embodiments. FIGS. 4A, 4B, and 4C are illustrations of MTJ film stacks, in accordance with various embodiments. FIG. 5 is a cross-sectional view of an SOT-MRAM device, in accordance with some embodiments. FIGS. 6 through 21 are intermediate steps used in formation of an SOT-MRAM device, in accordance with some embodiments. FIG. 22 is a cross-sectional view of an SOT-MRAM device, in accordance with some embodiments. FIG. 23 is a perspective view of an SOT-MRAM device, in accordance with some embodiments. FIG. 24 is a circuit diagram of an SOT-MRAM device according to some embodiments. FIG. 25 illustrates operations of an SOT-MRAM cell according to some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the Figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the Figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In addition, the term “made of” may mean either “comprising” or “consisting of.” Further, in the following fabrication process, there may be one or more additional operations in/between the described operations, and the order of operations may be changed. In the present disclosure, a phrase “one of A, B and C” means “A, B and/or C” (A, B, C, A and B, A and C, B and C, or A, B and C), and does not mean one element from A, one element from B and one element from C, unless otherwise described. Materials, configurations, dimensions, processes, and/or operations described with respect to one embodiment may be employed in the other embodiments, and detailed explanation thereof may be omitted. Embodiments use a synthetic free layer in an MTJ film stack instead of a single layer free layer. The synthetic free layer includes