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US-20260130122-A1 - WINDOW FABRICATION PROCESS FOR SUPERCONDUCTING QUBIT JUNCTIONS AND CROSSOVERS

US20260130122A1US 20260130122 A1US20260130122 A1US 20260130122A1US-20260130122-A1

Abstract

Described herein is a fabrication process for creating quantum devices including superconducting qubits, specifically Josephson tunnel junctions and crossovers. The process includes depositing and patterning a first metal layer on a qubit substrate to form the base structure of the circuit. A scaffolding layer is then applied, subsequently patterned and etched to create windows revealing the metal layer below. A thin insulating barrier is introduced within the window followed by the deposition of a second metal layer. This layered structure within the window forms a Josephson junction for the quantum bit. A second larger window serves to connect the Josephson junction to other devices within the circuit. The scaffolding layer is finally removed, creating an air gap in the circuit to isolate the first and second metal layers.

Inventors

  • John Matthew Martinis
  • Robert Francis McDermott, III
  • Alan Kar-Lun Ho

Assignees

  • Qolab, Inc.

Dates

Publication Date
20260507
Application Date
20241101

Claims (19)

  1. 1 . A method for fabricating a circuit comprising superconducting quantum bits, the method comprising: depositing a scaffolding layer on a first metal layer, the first metal layer patterned to define at least a first portion of the circuit comprising a superconducting quantum bit; creating a window in the scaffolding layer to provide access to the first metal layer by removing a volume of the scaffolding layer; creating a tunneling junction for the superconducting quantum bit in the window of the scaffolding layer; depositing a second metal layer in the window, wherein the second metal layer is patterned to form at least a second portion of the circuit comprising the superconducting quantum bit, and a layered structure of the first metal layer, the tunneling junction, and the second metal layer in the window of the scaffolding layer form a Josephson junction for the superconducting quantum bit of the circuit; and removing the scaffolding layer to create an air gap in the circuit between the first metal layer and the second metal layer outside of the Josephson junction.
  2. 2 . The method of claim 1 , further comprising: creating a third metal layer, the third metal layer patterned to form at least a third portion of the circuit, and wherein the second metal layer and the third metal layer form a crossover, wherein the air gap extends between the second metal layer and the third metal layer such that the second metal layer is suspended over the third metal layer.
  3. 3 . The method of claim 1 , wherein the window has a first dimension less than 0.3 um and a second dimension orthogonal to the first dimension less 0.3 um.
  4. 4 . The method of claim 1 , wherein the first metal layer and the second metal layer comprise aluminum.
  5. 5 . The method of claim 1 , wherein the scaffolding layer comprises silicon dioxide and a thickness of the scaffolding layer is 0.05 to 1 um.
  6. 6 . The method of claim 1 , wherein removing an area of the scaffolding layer to create the window comprises performing fluorine-based reactive ion etching on the scaffolding layer.
  7. 7 . The method of claim 1 , further comprising, after creating the window in the scaffolding layer, cleaning the second metal layer using an ion mill or plasma in a vacuum.
  8. 8 . The method of claim 7 , wherein cleaning the second metal layer using the ion mill or plasma comprises using argon for the ion mill or plasma.
  9. 9 . The method of claim 1 wherein creating the tunneling junction comprises depositing the second metal layer in the window without an oxidation step.
  10. 10 . The method of claim 1 , wherein the scaffolding layer comprises high-density silicon dioxide having a wet etch ratio for hydrofluoric acid less than 3.
  11. 11 . The method of claim 1 , wherein removing the scaffolding layer to create the air gap comprises etching the scaffolding layer using a hydrofluoric acid vapor.
  12. 12 . The method of claim 1 , wherein the window comprises a wall angle from 65 to 85 degrees.
  13. 13 . A quantum circuit comprising: a first metal layer patterned to form at least a first portion of the circuit; a second metal layer patterned to form at least a second portion of the circuit; and a superconducting quantum bit comprising: a Josephson junction comprising a layered structure, the layered structure comprising an area of the first metal layer, a tunneling junction, and an area of the second metal layer; and wherein the Josephson junction is formed in a window of a scaffolding layer deposited on the first metal layer; and wherein an air gap is formed within the quantum circuit between the first metal layer and the second metal layer by removing the scaffolding layer outside of the Josephson junction.
  14. 14 . The quantum circuit of claim 13 , further comprising: a third metal layer, the third metal layer patterned to form at least a third portion of the circuit, and wherein the second metal layer and the third metal layer form a crossover, wherein the air gap extends between the second metal layer and the third metal layer such that the second metal layer is suspended over the third metal layer.
  15. 15 . The quantum circuit of claim 13 , wherein the window has a first dimension less than 0.3 um and a second dimension orthogonal to the first dimension less 0.3 um.
  16. 16 . The quantum circuit of claim 13 , wherein the first metal layer and the second metal layer comprise aluminum.
  17. 17 . The quantum circuit of claim 13 , wherein the scaffolding layer comprises high-density silicon dioxide having a wet etch ratio for hydrofluoric acid less than 3.
  18. 18 . The quantum circuit of claim 13 , wherein the window has a first dimension less than 0.3 um and a second dimension orthogonal to the first dimension less 0.3 um.
  19. 19 . The method of claim 1 , wherein the window comprises a wall angle from 65 to 85 degrees.

Description

BACKGROUND Field of Disclosure This invention relates generally to quantum computing, and more particularly to the fabrication of superconducting qubits for greater coherence and reliability. Description of Related Art Quantum computers perform calculations that cannot be run by classical supercomputers, such as efficient prime factorization or solving how molecules bind using quantum chemistry. Quantum computers can be made from a variety of physical systems such as superconducting qubits, trapped ion systems, photonic systems, etc. An advantage of superconducting qubits is that they can be fabricated using standard integrated-circuit technology, enabling scaling of the number of qubits to large size similar to their conventional electronics counterparts. Although superconducting qubits use thin-film deposition and etch equipment that is common to typical fabrication processing like CMOS, special processes are necessary for good qubit performance. In particular, dielectrics like amorphous silicon dioxide have large energy loss at low temperature and are generally not compatible with quantum computing devices. This identified deficiency is important because a critical component called the Josephson tunnel junction, which gives a non-linear inductance crucial for producing useful quantum states, is typically fabricated with a lift-off process. Lift off processes oftentimes leave residue and rough edges that can degrade qubit coherence. In some fabrication processes, a lift-off process is not used, but instead the process employs a second crossed metal wire for the junction. However, this process requires a cleaning step that produces amorphous silicon underneath this electrode, which introduces additional energy loss. Accordingly, a fabrication process for Josephson junction superconducting qubits that avoids traditional lift-off processes would be beneficial. SUMMARY A technique to create a quantum computing device using lithographic processes is described. In particular, the Specification and Drawings describe a process to create Josephson junctions and crossover wiring contacts that uses standard processing steps of deposition and etch. The selected processing steps are reliable and are demonstrated in conventional CMOS electronics for devices with billions of transistors. The described device and fabrication process are superior to devices and methods employing present-day lift-off processes, which show qubit dropouts even at the scale of 50-100 qubits. For the described process, etching the metal gives clean edges instead of a diffuse edge with many small metal islands that are produced during a lift-off process. The etching process described herein lessens the number of surface defects such as, e.g., the two-level states that degrade coherence relative to the traditional number of surface defects generated by the lift-off process. In addition, the Josephson junction area is defined by a window etched into a sacrificial layer of silicon dioxide. The etching process to create the window is conducted using the same process step to create vias in standard CMOS processing. Since vias are a critical process step in complex integrated-circuit processing, the parameters for via etch are well known and thus the window area can be controlled reliably. This enables better control of the Josephson junction critical current, a key parameter for making qubits with the correct transition frequency. During fabrication of the quantum device, silicon dioxide acts as a scaffold for the Josephson junction and crossovers, and is removed before using the device (because, if it remained, the material would cause a large loss in the device). Silicon dioxide is chosen because it can be etched with vapor HF, which does not collapse the resulting bridge structure since it etches in a vapor phase without liquid surface tension. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 shows a cross-section view of a quantum device fabricated using the disclosed process, according to an example embodiment. FIG. 2 shows a cross-section view of a quantum device fabricated using the disclosed process and including a crossover electrode, according to an example embodiment. FIG. 3 illustrates a workflow diagram for fabricating a circuit comprising superconducting quantum bits, according to an example embodiment. The figures depict various embodiments for purposes of illustration only. One skilled in the art will readily recognize from the following discussion that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles described herein. DETAILED DESCRIPTION As described above, fabricating quantum devices such as, e.g., a Josephson tunnel junction for a superconducting qubit without traditional lithography lift-off processes is beneficial because the resulting devices have better performance than those fabricated using lift-off processes. FIG. 1 shows a cross-section view of a quantum de