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US-20260130124-A1 - PLANAR ELECTRICALLY FLOATING QUBIT CIRCUIT STRUCTURE

US20260130124A1US 20260130124 A1US20260130124 A1US 20260130124A1US-20260130124-A1

Abstract

A planar electrically floating qubit circuit structure including a Josephson junction region galvanically coupled to first and second electrode regions and a ground electrode region is configured so as to result in a series capacitance of the first and second electrode regions to the ground electrode region that is greater than the self-capacitance of the Josephson junction region.

Inventors

  • Rami Barends

Assignees

  • Forschungszentrum Jülich GmbH

Dates

Publication Date
20260507
Application Date
20231010
Priority Date
20221011

Claims (20)

  1. 1 - 19 . (canceled)
  2. 20 . A planar electrically floating qubit circuit structure, comprising: a Josephson junction region including first and second weakly coupled superconductors; first and second electrode regions galvanically coupled to said first and second superconductors, respectively; and a ground electrode region; wherein a series capacitance of said first and second electrode regions to said ground electrode region is greater than a self-capacitance of said Josephson junction region.
  3. 21 . The circuit structure according to claim 20 , wherein said Josephson junction region has a surface area that is less than a surface area of each of said first and second electrode regions.
  4. 22 . The circuit structure according to claim 21 , wherein said first and second electrode regions have a geometrical arrangement that is centrally symmetric with respect to a centroid of the surface area of said Josephson junction region.
  5. 23 . The circuit structure according to claim 20 , wherein each of said first and second electrode regions is shaped as a continuous strip of essentially uniform width that extends between a connecting portion thereof, which is located adjacent to said Josephson junction region for galvanic connection thereto, and at least one free end portion thereof, which is located remote from said Josephson junction region.
  6. 24 . The circuit structure according to claim 23 , wherein said at least one free end portion includes first and second free end portions, said connecting portion of said strip being located half-way therebetween.
  7. 25 . The circuit structure according to claim 24 , wherein directions of extension of said strip from the connecting portion to the first and second free end portions are essentially mutually orthogonal.
  8. 26 . The circuit structure according to claim 24 , wherein a direction of extension of said strip is a mean linear direction, said strip meandering about said linear direction between said connecting portion thereof and each one of said free end portions thereof.
  9. 27 . The circuit structure according to claim 20 , wherein said ground electrode region and each of said first and second electrode regions is arranged so as to form a microstrip waveguide.
  10. 28 . The circuit structure according to claim 20 , wherein said ground electrode region and each of said first and second electrode regions is arranged so as to form a coplanar waveguide.
  11. 29 . The circuit structure according to claim 20 , wherein said qubit circuit is a fixed-frequency transmon or a tuneable transmon.
  12. 30 . A combination, comprising: a tuneable coupler; and two circuit structures according to claim 20 , wherein at least one of said first and second electrode regions of one of said two circuit structures is capacitively coupled to the tuneable coupler that is capacitively coupled to one of said first and second electrode regions of the other one of said two circuit structures.
  13. 31 . The combination according to claim 30 , wherein each of said first and second electrode regions is shaped as a continuous strip of essentially uniform width that extends between a connecting portion thereof, which is located adjacent to said Josephson junction region for galvanic connection thereto, and at least one free end portion thereof, which is located remote from said Josephson junction region, wherein said at least one free end portion of said strip forming one of said first and second electrode regions of said one of said two circuit structures and said at least one free end portion of said strip forming one of said first and second electrode regions of said other one of said two circuit structures are located adjacent to said coupler for capacitive coupling thereto.
  14. 32 . The combination according to claim 31 , wherein a distance between said free end portions is dimensioned so as to result in a desired value of the capacitive coupling.
  15. 33 . The combination according to claim 31 , wherein the strips that extend between said connecting portions and said at least one free end portions extend along a common linear center line.
  16. 34 . The combination according to claim 30 , further comprising a third electrode region that is capacitively coupled to said common ground electrode region and to said first and second electrode regions that are capacitively coupled to said tuneable coupler, wherein said tuneable coupler is connected to the third electrode region, said third electrode region being dimensioned so as to result in desired values of self-capacitance of the tuneable coupler and the coupling capacitances between said one and said other one of said qubit circuit structures and said tuneable coupler, respectively.
  17. 35 . The combination according to claim 34 , wherein said third electrode region extends adjacent to and along the strips whose free end portions are located adjacent to said coupler.
  18. 36 . The combination according to claim 35 , wherein the third electrode region is shaped as a strip of essentially uniform width that longitudinally extends alongside the strips whose free end portions are located adjacent to said coupler.
  19. 37 . The combination according to claim 35 , wherein the third electrode region is shaped as first and second strips of essentially uniform width that longitudinally extend on both sides alongside the strips whose free end portions are located adjacent to said coupler.
  20. 38 . The circuit structure according to claim 30 , wherein said ground electrode region and at least one of said first and second electrode regions, respectively, extend in a common plane with adjacent boundaries thereof so as to define an insulating gap therebetween.

Description

The invention relates to a planar electrically floating qubit circuit structure comprising a Josephson junction region including first and second weakly coupled superconductors; first and second electrode regions galvanically coupled to said first and second superconductors, respectively; and a ground electrode region. Quantum circuits including a Josephson junction having a self-capacitance and an external shunt capacitance connected thereacross are generally known. In particular, transmon qubits that are currently widely used are generally implemented using a dominant direct capacitor in parallel with either a single Josephson junction for fixed-frequency qubits, or two Josephson junctions in a superconducting quantum interference device (SQUID) geometry. These qubits are straight forward to build, however, they suffer from a lack of coherence. To remedy the coherence problem, it has been a conventional approach to use extended, large capacitors directly connected across the superconductors of the Josephson junction. In this case, the electric fields are low so that individual coupling to defects in the capacitive area is minimised. This can, however, induce parasitic couplings in large systems. Moreover, using such large capacitors complicates implementing coupling schemes between qubits, resonators, and other elements, due to the size needed for coupling capacitors. An article entitled “Merged-element transmon” published by R. Zhao, S. Park, T. Zhao, M. Bal, C. R. H. McRae, J. Long, and D. P. Pappas (Phys. Rev. Applied 14, 064006 (2020)) proposes to implement the circuit structure by engineering the Josephson junction self-capacitance to be large enough to act as its own shunt capacitor, thereby eliminating the need for the external direct capacitor. It is an object of the present invention to propose an alternative implementation of a qubit circuit structure of the above referenced type. In order to attain this object, a circuit structure of the above referenced type is implemented with the series capacitance of said first and second electrode regions to said ground electrode region being greater than the self-capacitance of said Josephson junction region. In the planar circuit structure of the invention, the first and second electrode regions are mutually galvanically isolated and each of them is also galvanically isolated from the coplanar ground electrode. In particular, the isolation is effected by an isolation zone that is free from electrode material and is located between the ground electrode region and the first and second electrode regions so as to physically separate them from each other. This is preferably realized by a thin metallization layer formed on the plain surface of an underlying substrate and having cut-outs formed therein that spatially separate the ground electrode region and the first and second electrode regions from each other. In particular, these cut-outs are in the shape of thin strips that are free of metallization material. In this configuration, capacitances between the ground electrode region and the first and second electrode regions, respectively, form a series capacitance that shunts the self-capacitance of the Josephson junction region. The capacitance value of this arrangement may be calculated in accordance with a method disclosed in arXiv:1410.3458 entitled “Calculation of Coupling Capacitance in Planar Electrodes”. The circuit structure according to the invention is configured so as to result in a value of the series capacitance that is greater than the value of the self-capacitance of the Josephson junction region. In practice, the proportion of the self-capacitance in the total capacitance may be not more than 40%, preferably not more than 30%, or 20% or even 10%. As compared to prior art using a dominant direct capacitor in parallel with a Josephson junction, the circuit structure according to the invention results in better coherence. There is less coupling to individual dipole defects (as for instance described in an article by J. M. Martinis, K. B. Cooper, R. McDermott, M. Steffen, M. Ansmann, K. D. Osborn, K. Cicak, S. Oh, D. P. Pappas, R. W. Simmonds, and C. C. Yu, Phys. Rev. Lett. 95, 210503 (2005) entitled “Decoherence in Josephson Qubits from Dielectric Loss”), as it requires more ground capacitance and hence less electrical field strength. It is easier to implement coupling to drivelines, qubits or other elements, as the implementation has longer traces. In addition, parasitic crosstalk to other qubits is reduced. Larger distance between the qubits means that qubits are farther away from the other qubits “center of mass”. Further, parasitic coupling and related loss to other grounds and metals on other planes for 3D-integrating systems is reduced thanks to the direct capacitance to ground. The circuit structure according to the invention can be straight forwardly implemented using waveguides, and the parasitic inductance is small. The invention is no