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US-20260130126-A1 - SCALABLE WIRING OF SUPERCONDUCTING QUBITS WITH SILICON WAFERS

US20260130126A1US 20260130126 A1US20260130126 A1US 20260130126A1US-20260130126-A1

Abstract

A quantum computing system with structures for wiring superconducting qubits between varying thermal regimes is presented. This system enables the control of many thousands to millions of qubits operated at typical qubit operating temperatures, while the control electronics operate at much higher temperatures, such as 3-4 K, 50-77 K, or 300 K. The system includes a qubit substrate with one or more qubits, a metallization layer, a wiring substrate comprising superconducting striplines, a mechanical mount, and a quantum computing device. The system includes structures disposed throughout that connect a lower temperature section for qubit operation to a higher temperature section for control operations. The system also employs flex circuit boards for achieving dense and scalable connectivity. Methods for fabricating the quantum computing system are also disclosed.

Inventors

  • John Matthew Martinis
  • Robert Francis McDermott, III
  • Alan Kar-Lun Ho

Assignees

  • Qolab, Inc.

Dates

Publication Date
20260507
Application Date
20241003

Claims (20)

  1. 1 . A wiring system for a quantum computer comprising: a qubit substrate comprising a plurality of qubits in a first thermal environment; one or more control electronics in a second thermal environment warmer than the first thermal environment; and a wiring substrate comprising a plurality of transmission lines created using lithography processes, the plurality of transmission lines electrically connecting the plurality of qubits in the first thermal environment to the one or more control electronics in the second thermal environment warmer than the first thermal environment.
  2. 2 . The wiring system of claim 1 , wherein each quantum bit of the plurality of qubits comprise superconducting quantum devices.
  3. 3 . The wiring system of claim 1 wherein the first thermal environment has a temperature of less than 50 mK, and the second thermal environment has a temperature greater than 1K and less than 10 K.
  4. 4 . The wiring system of claim 1 , wherein the wiring substrate comprises one or more thinned sections structured such that they thermally isolate the first thermal environment from the second thermal environment.
  5. 5 . The wiring system of claim 4 , wherein a thinned section of the one or more thinned section comprises a surface with a surface roughness between 10 nm and 10 um, the surface roughness configured to reduce thermal conductivity in the wiring substrate.
  6. 6 . The wiring system of claim 4 , wherein a thickness of the wiring substrate is between 100 um and 2 mm, and a thickness of the one or more thinned sections is between 100 nm and 50 um.
  7. 7 . The wiring system of claim 4 , wherein the one or more thinned sections comprises a window within the wiring substrate comprising a plurality of ribs, the plurality of ribs providing mechanical strength to the wiring substrate.
  8. 8 . The wiring system of claim 1 , wherein the plurality of qubits of the qubit substrate, the plurality of transmission lines, and the wiring substrate are fabricated using one or more of a lithography process and an etching process.
  9. 9 . The wiring system of claim 1 , wherein the qubit substrate comprises two or more separate qubit substrates, each of the two or more separate qubit substrates comprising one or more of the plurality of qubits.
  10. 10 . The wiring system of claim 9 , wherein at least a pair of separate qubit substrates of the two or more separate qubit substrates are tiled together to form the qubit substrate.
  11. 11 . The wiring system of claim 10 , wherein qubits on the pair of separate qubit substrates are capacitively coupled to one another.
  12. 12 . The wiring system of claim 10 , wherein the pair of separate quantum bit substrates are held in place with a mechanical frame.
  13. 13 . The wiring system of claim 1 , wherein the qubit substrate is electrically connected to the wiring substrate with a bump bond.
  14. 14 . The wiring system of claim 1 , wherein a transmission line of the plurality of transmission lines comprises a superconducting material with a critical transition temperature greater than 4 K.
  15. 15 . The wiring system of claim 1 , wherein a transmission line of the plurality of transmission lines comprises a layer of superconducting material electrically isolated from other transmission lines of the plurality of transmission lines by an insulator.
  16. 16 . The wiring system of claim 1 , wherein each transmission line of the plurality of transmission lines has a width between 2 nm and 1 um.
  17. 17 . The wiring system of claim 16 , wherein each transmission line of the plurality of transmission lines is electrically connected to a corresponding wiring electrode of a plurality of wiring electrodes on the wiring substrate, and each wiring electrode of the plurality of wiring electrodes has a width between 50 nm and 5 um.
  18. 18 . The wiring system of claim 1 , wherein a transmission line of the plurality of transmission lines comprises a low pass filter with a low-pass cutoff frequency between 0.1 and 10 GHz.
  19. 19 . The wiring system of claim 1 , wherein the qubit substrate comprises at least 1000 qubits.
  20. 20 . The wiring system of claim 1 , wherein the wiring substrate comprising a plurality of transmission lines created using lithography processes comprises at least 1000 transmission lines.

Description

BACKGROUND Field of Disclosure This invention relates generally to quantum computing, and more particularly to the wiring of superconducting qubits to higher-temperature control circuitry using silicon wafers. Description of Related Art Quantum computers perform calculations that cannot be run by classical supercomputers, such as efficient prime factorization or solving how molecules bind using quantum chemistry. The most difficult problems can only be solved by embedding the algorithm in a large quantum computer that is running quantum error correction. However, this requires the control of many thousands to millions of qubits, and the power budget for such a system typically constrains the control signals to be generated by electronics that are at a much higher temperature than the qubits themselves. For example, the qubits are typically operated at about 20 mK, whereas the control electronics can be at temperature stages of 3-4 K, 50-77 K or 300 K. In turn, wiring must be used to connect the qubits operating at low temperatures to control electronics operating at higher temperatures. Although coaxial wiring has been used successfully in the past few decades, this solution is not expected to be scalable to the many thousands to millions of wires that will be needed for a large quantum computer. A solution is needed that both retains the electrical integrity of the signals, but can be densely packed, fabricated and assembled at reasonable cost. To illustrate this difficulty, the permissible thermal load at the qubit temperature is low, less than 1 mW, whereas at higher temperatures the thermal load is significantly higher, roughly 20 W at 3-4K, 1 kW at 77K, and greater than 10 kW at 300K. Due to the different thermal and electrical physics over this large temperature range, different wiring solutions from 20 mK to 3 K, and then from 3 K and higher are worthwhile. SUMMARY The systems and method herein describe a wiring solution from 20 mK to 3-4 K (and possibly from 3-4 K and higher) using superconducting wiring. The wiring is fabricated using photolithographic technology on large 300 mm Silicon wafers. Superconductivity allows the use of transmission-line wiring with small dimensions without introducing electrical damping and waveform distortion of the control signals. Small dimensions in this case indicate sizes on the order of 1 micrometer (um), such as, e.g., 20 nanometers (nm), 50 nm, 100 nm, 250 nm, 500 nm, 1 um, 5 um, 10 um, etc. Dense writing can be fabricated using traditional integrated circuit technology. Even though there may be many thousands of wires, the low thermal conductance of superconductors gives low heat loads to low temperature, providing thermal isolation. Notably, however, the additional, strong thermal conductivity comes from the Silicon wafer, which is much thicker (e.g., 775 um) than the superconducting wiring layer (e.g., 1 um). To reduce the thermal conductivity, one or more portions of the Silicon wafer are processed (e.g., micromachined, lithography processes, etc.) to reduce its thickness to about 0.1-50 um using an etching process, where the thinned sections (e.g., windows) are lithographically defined. By using thermal anchoring at intermediate temperature stages of 1K or below, the resulting heat load to the qubits at 20 mK can be made acceptably low. In other words, the silicon wafer is fabricated to create a series of thermally isolated sections that reduce the thermal load of wires connecting higher temperatures to lower temperatures. Additionally, the transmission-line wiring typically employs filtering of electrical signals above about 1 GHz to reduce thermal noise coming from higher temperatures, which would produce errors in the qubits. To this end, a compact transmission-line filter that is compatible with the dense wiring for the disclosed wiring solution is also described. The wires can be brought out to pads at 3-4 K to connect to electronics at this stage, as well as to wiring to higher temperatures. Because there are no easily fabricated superconductors at temperatures above 3-4 K, flex wiring is fabricated using a Copper alloy fabricated in a conventional means using well understood fabrication techniques. The flex wiring can be connected to the Silicon substrate at 3-4 K using conventional spring connectors, since the small resistance of the connector (1-10 mOhms) produces only a small heat load at 3-4 K. Such power loss at the qubit temperature is detrimental to device function, and thus the Silicon wiring provides a method to readily connect to the qubits without thermal loading. The fabrication technology of this Silicon wiring is generally different than needed for the superconducting qubits. As such, a dense array of bump bonds, made from superconducting indium, are fabricated to connect qubits from a qubit wafer (e.g., made from 200 millimeter (mm) or 300 mm processes) to the a wiring wafer (e.g., made from 200 mm or 300 mm processes). Thus, wires for