US-20260130135-A1 - GROWTH SUBSTRATE WAFER FOR HIGH-PERFORMANCE GAN SWITCHING POWER DEVICES, EPITAXY WAFER USING THE SAME, AND MANUFACTURING METHOD THEREOF

US20260130135A1US 20260130135 A1US20260130135 A1US 20260130135A1US-20260130135-A1

Abstract

Embodiments according to the present invention provide a growth substrate wafer for high-performance GaN switching power devices, comprising: a Si growth substrate; a first AlN nucleation layer formed on the Si growth substrate; and a plurality of SiOx protrusions (Protrusion) discontinuously spaced apart and arranged on the first AlN nucleation layer, wherein the surface of the first AlN nucleation layer is exposed in the regions between the plurality of SiOx protrusions.

Inventors

June O Song
Jihyung Moon
Younghun HAN
Hyun Sun YUN

Assignees

WAVELORD CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20251104
Priority Date: 20241105

Claims (11)

1 . A growth substrate wafer for high-performance GaN switching power devices, comprising: a Si growth substrate; a first AlN nucleation layer formed on the Si growth substrate; and a plurality of SiOx protrusions discontinuously spaced apart and arranged on the first AlN nucleation layer, wherein the surface of the first AlN nucleation layer is exposed in the regions between the plurality of SiOx protrusions, a growth substrate wafer for high-performance GaN switching power devices.
2 . The growth substrate wafer of claim 1 , wherein the shape of the SiOx protrusions is a Lens, Truncated, Dome, Cone, Polygon, or Cubic shape.
3 . The growth substrate wafer of claim 1 , further comprising a SiNx protective film formed between the first AlN nucleation layer and the plurality of SiOx protrusions.
4 . An epitaxy wafer using the growth substrate wafer of any one of claim 1 , comprising: a GaN-based merged growth layer grown from the exposed surface of the first AlN nucleation layer between the plurality of SiOx protrusions, covering the top of the SiOx protrusions and merging with each other; and a GaN HEMT device active layer formed on the GaN-based merged growth layer.
5 . The epitaxy wafer of claim 4 , wherein the GaN-based merged growth layer is a single layer of undoped GaN (uGaN).
6 . The epitaxy wafer of claim 4 , wherein the GaN-based merged growth layer is a multilayer structure in which uGaN layer and AlN layer or AlGaN layer are alternately stacked.
7 . The epitaxy wafer of claim 4 , further comprising an Al(z)Ga(1-z)N stress control layer formed between the GaN-based merged growth layer and the GaN HEMT device active layer.
8 . The epitaxy wafer of claim 4 , further comprising a second AlN nucleation layer formed between the plurality of SiOx protrusions and the GaN-based merged growth layer, and covering the exposed surface of the first AlN nucleation layer and the surface of the SiOx protrusions.
9 . A method for manufacturing an epitaxy wafer using a growth substrate wafer for high-performance GaN switching power devices, comprising the steps of: (a) preparing a Si growth substrate; (b) forming a first AlN nucleation layer on the Si growth substrate; (c) depositing a SiOx thin film on the first AlN nucleation layer; (d) patterning the SiOx thin film to form a plurality of discontinuously spaced SiOx protrusions; (e) forming a GaN-based merged growth layer by laterally growing (Epitaxial Lateral Overgrowth, ELOG) a GaN-based material from the first AlN nucleation layer exposed between the SiOx protrusions and merging them over the SiOx protrusions; and (f) stacking a GaN HEMT device active layer on the GaN-based merged growth layer.
10 . The method of claim 9 , wherein said step (e) comprises forming the GaN-based merged growth layer by alternately and repeatedly growing uGaN layer and one of AlN layer and AlGaN layer.
11 . The method of claim 9 , further comprising a step of forming a second AlN nucleation layer on the first AlN nucleation layer and the plurality of SiOx protrusions, between said step (d) and step (e).

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit and priority to Korean Patent Application Nos. 10-2024-0154847, filed on Nov. 5, 2024 and 10-2025-0163805, filed on Nov. 4, 2025. The entire disclosures of the applications identified in this paragraph are incorporated herein by references. FIELD The present invention relates to a high-performance switching power device (Switching Power Device) using gallium nitride (GaN), and more particularly, to a patterned silicon substrate (PSiS, Patterned Si Substrate) for forming a high-quality GaN epitaxial layer on a silicon (Si) growth substrate, and an epitaxy wafer and manufacturing method thereof, which dramatically reduces the Threading Dislocation Density (TDD) using said substrate. BACKGROUND Gallium nitride (GaN) compound semiconductor is a wide-bandgap material that has a higher breakdown field, excellent thermal conductivity, and high carrier mobility compared to conventional semiconductor materials such as silicon (Si) and gallium arsenide (GaAs). Thanks to these characteristics, it can implement high power density in a smaller size and is drawing attention as a key material for next-generation power semiconductor devices. For GaN power semiconductors to be competitive in the market, Normally-OFF operation with a high blocking voltage and low leakage current is essential. The most ideal structure to implement this is a vertical structure device (Vertical FET) with a thick epitaxial region, but due to the difficulty in commercializing GaN homogenous growth substrates (GaN-on-GaN) and the low efficiency of the ion implantation process, horizontal structure High Electron Mobility Transistors (HEMTs) that grow a thin film on a heterogeneous growth substrate are currently mainly being manufactured. At this time, heterogeneous growth substrates such as sapphire, silicon (Si), and silicon carbide (SiC) are used, but a very high threading dislocation density (TDD) on the level of 107˜1010/cm2 occurs due to the lattice constant and thermal expansion coefficient mismatch between the GaN epitaxial layer and the growth substrate. These threading dislocations are a persistent problem that critically and adversely affects device performance and reliability. Specifically, threading dislocations cause various problems as follows. (1) Increased Leakage Current: Threading dislocations containing screw components (Screw and Mixed Dislocations) act as major leakage paths, degrading the device's Off-state characteristics.(2) Reduced Blocking Voltage: Threading dislocations act as ‘hotspots’ that cause Electric Field Crowding at specific points within the device, leading to Premature Breakdown before the device reaches its inherent breakdown voltage.(3) Decreased Switching Frequency: Threading dislocations act as scattering and trapping centers in the electron's movement path, reducing carrier mobility. This performance degradation is particularly prominent in horizontal HEMT structures where current flows laterally to the threading dislocations.(4) Increased Dynamic On-resistance (RON): During high-voltage switching operation, charge is trapped in defects, including threading dislocations, and then slowly released, causing a phenomenon where the on-resistance temporarily increases immediately after the switch is turned on. This is a major cause of increased power loss.(5) Decreased Reliability: Crystal defects such as threading dislocations become the starting point for various degradation mechanisms such as gate edge degradation, hot electron generation, and thin-film delamination when the device operates in high electric field and temperature environments, thereby shortening the device's lifespan. Therefore, to commercialize high-performance, high-reliability GaN power devices, the development of high-quality epitaxial growth technology capable of controlling TDD to less than 108/cm2 on large-diameter 8-inch or 12-inch Si substrates is urgently required. SUMMARY Technical Problem The present invention was devised to solve the problems of the conventional art as described above, and its main object is to solve the high threading dislocation density (TDD) problem that occurs when growing a GaN epitaxial layer on a large-diameter silicon (Si) growth substrate. Specifically, an object of the present invention is to dramatically reduce TDD to less than 108/cm2 to provide a high-quality GaN HEMT epitaxy wafer that can improve electrical characteristics such as leakage current and dynamic ON-resistance, and enhance breakdown voltage and reliability. Furthermore, another object of the present invention is to provide a growth substrate wafer for high-performance GaN power devices and a manufacturing method thereof, which is applicable to 8-inch and 12-inch large-diameter wafer processes, offering high productivity and cost-effectiveness. Technical Solution Embodiments according to the present invention provide a growth substrate wafer for high-performance G