US-20260130140-A1 - PLANARIZATION PROCESS WITH LASER TREATMENT

Abstract

A method includes forming a first layer over a second layer; performing a laser treatment process on the first layer, wherein the laser treatment process includes directing a laser beam into the first layer, wherein the laser beam modifies the first layer; and after performing the laser treatment process on the first layer, performing a planarization process on the first layer to remove the first layer, wherein the planarization process exposes the second layer.

Inventors

• Jhih Guang WU
• Chih Hung Chen
• Jin-Hao JHANG

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date

20260507

Application Date

20250307

Claims (20)

1. 1 . A method comprising: forming a first layer over a second layer; performing a laser treatment process on the first layer, wherein the laser treatment process comprises directing a laser beam into the first layer, wherein the laser beam modifies the first layer; and after performing the laser treatment process on the first layer, performing a planarization process on the first layer to remove the first layer, wherein the planarization process exposes the second layer.
2. 2 . The method of claim 1 , wherein a focal point of the laser beam is above a top surface of the second layer.
3. 3 . The method of claim 1 , wherein the laser beam has a wavelength in the range of 300 nm to 1500 nm.
4. 4 . The method of claim 1 further comprising: forming a stack of nanostructures over a substrate, wherein the stack of nanostructures comprises the second layer, wherein forming the first layer comprises depositing the first layer over the stack of nanostructure and on sidewalls of the nanostructures of the stack of nanostructures; and after performing the planarization process, forming a gate structure between neighboring nanostructures of the stack of nanostructures.
5. 5 . The method of claim 1 , wherein the first layer is silicon.
6. 6 . The method of claim 1 , wherein the first layer and the second layer are a same material.
7. 7 . The method of claim 1 , wherein after performing the laser treatment process, the entire first layer is modified.
8. 8 . The method of claim 1 , wherein the laser beam modifies the first layer by heating the first layer.
9. 9 . The method of claim 1 , wherein the planarization process is a chemical mechanical polishing (CMP) process.
10. 10 . A method comprising: depositing a first layer over a substrate, wherein the first layer is a first material; and removing an upper portion of the first layer, comprising: scanning a laser beam across a top surface of the first layer, wherein after scanning the laser beam, the upper portion of the first layer has different physical properties than an underlying lower region of the first layer; and polishing the upper portion of the first layer to expose the lower region of the first layer.
11. 11 . The method of claim 10 , wherein a focal point of the laser beam is located a first depth into the first layer, wherein the first depth is less than a first thickness of the first layer.
12. 12 . The method of claim 10 , wherein, after scanning the laser beam, a polishing removal rate of the upper region is greater than a polishing removal rate of the lower region.
13. 13 . The method of claim 10 , wherein first material is an oxide.
14. 14 . The method of claim 10 , wherein the laser beam is pulsed during scanning of the laser beam.
15. 15 . The method of claim 10 , wherein after scanning the laser beam, the upper portion of the first layer has a larger volume than the upper portion of the first layer prior to scanning the laser beam.
16. 16 . The method of claim 10 further comprising depositing a second layer over the substrate, wherein the first layer covers the second layer, wherein polishing the upper portion of the first layer also exposes the second layer.
17. 17 . A method comprising: forming a first bonding layer over a first substrate; forming a second bonding layer over a second substrate; bonding the first bonding layer to the second bonding layer using a fusion bonding process; heating the first substrate using a first laser; and removing the first substrate using a first mechanical planarization process.
18. 18 . The method of claim 17 , wherein the first substrate is a silicon wafer.
19. 19 . The method of claim 17 further comprising: forming a dielectric material over the second substrate; heating an upper portion of the dielectric material using a second laser; and removing the upper portion of the dielectric material using a second mechanical planarization process.
20. 20 . The method of claim 17 further comprising forming a multi-layer stack between the first bonding layer and the first substrate, wherein removing the first substrate exposes the multi-layer stack.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This application claims the benefit of the following provisionally filed U.S. Patent application: Application No. 63/715,023, filed on Nov. 1, 2024, which application is hereby incorporated herein by reference. BACKGROUND Semiconductor devices are used in a variety of electronic applications such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. During the formation of higher-density semiconductor devices, uneven topography of layers can affect yield and device performance. Thus, improved techniques to improve the planarity of layers are desired. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1, 2, 3, 4, 5, and 6 illustrate intermediate stages in the performing of a planarization process including a laser treatment process, in accordance with some embodiments. FIGS. 7, 8, 9, and 10 illustrate intermediate stages in the performing of a planarization process including a laser treatment process, in accordance with some embodiments. FIG. 11 illustrates a three-dimensional view of example Complementary Field-Effect Transistors (CFETs), in accordance with some embodiments. FIGS. 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, and 27 are various views of intermediate stages in the manufacturing of CFETs, in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Various representative embodiments are described with respect to performing a planarization process to remove material or to planarize the surface of a layer. The embodiments described herein include a laser treatment process performed on the material prior to removal by the planarization process. The laser treatment process modifies the material, allowing the material to be more easily removed by the planarization process. This can allow for more accurate material removal and can allow for improved planarity of the resulting planarized surface. For example, performing a laser treatment process can reduce the effects of initial surface topography on the planarization process, allowing for improved uniformity, reduced dishing, and improved flatness of the resulting planarized surface. The embodiments described herein are intended as illustrative and non-limiting examples, and all suitable variations, materials, applications, manufacturing steps, devices, or structures are considered within the scope of the present disclosure. FIGS. 1 through 6 illustrate intermediate steps in a planarization process including a