US-20260130147-A1 - ROBUST EASILY-REMOVED ETCH STOP

Abstract

Embodiments of the disclosure are directed to an integrated circuit (IC) that includes a transistor, a dielectric region and an etch stop material. A portion of the etch stop material is between a portion of the dielectric region and a portion of a gate spacer material of the transistor. The etch stop material is soluble responsive to an etch stop removal material selected from the group consisting of water and an acid.

Inventors

• Aakash Pushp
• Teya Topuria
• Eugene Delenia
• Oleg Gluschenkov
• Noel Arellano
• Slavko N. Rebec
• Rishikesh Krishnan
• Paul Charles Jamison
• Ishwar Singh
• Holt Bui
• Anthony Bock Fong

Assignees

• INTERNATIONAL BUSINESS MACHINES CORPORATION

Dates

Publication Date

20260507

Application Date

20241105

Claims (20)

1. 1 . An integrated circuit (IC) comprising: a transistor; a dielectric region; and an etch stop material; wherein a portion of the etch stop material is between a portion of the dielectric region and a portion of a gate spacer material of the transistor; and wherein the etch stop material is soluble responsive to an etch stop removal material selected from the group consisting of water and an acid.
2. 2 . The IC of claim 1 , wherein: the acid comprises a weak acid; and the weak acid comprises an acid dissociation constant (Ka) at or below about 1×10 −5 .
3. 3 . The IC of claim 1 , wherein: the transistor comprises a source or drain (S/D); the S/D is formed in a S/D trench; the gate spacer material has a first etch rate responsive to an etchant used to form the S/D trench; the etch stop material has a second etch rate responsive to the etchant used to form the S/D trench; and the second etch rate is less than the first etch rate.
4. 4 . The IC of claim 3 , wherein the etch stop material comprises a vapor pressure at or below a predetermined vapor pressure level.
5. 5 . The IC of claim 4 , wherein the predetermined vapor pressure level is about 1 Torr.
6. 6 . The IC of claim 3 , wherein the etch stop material further comprise a boiling point above a predetermined boiling point.
7. 7 . The IC of claim 6 , wherein the predetermined boiling point is above 1300 degrees Celsius.
8. 8 . The IC of claim 3 , wherein the etch stop material is selected from the group consisting of a magnesium-containing material and a calcium-containing material.
9. 9 . The IC of claim 3 , wherein: the transistor further comprises a bottom dielectric; the portion of the etch stop material is between the portion of the dielectric region and a portion of the S/D; and the bottom dielectric is between the portion of the etch stop material and a portion of the S/D.
10. 10 . An integrated circuit (IC) fabrication method comprising: forming an etch stop material, wherein a portion of the etch stop material is adjacent a gate spacer of a transistor-under-fabrication (TUF); forming a dielectric region over and adjacent to the portion of the etch stop material; and applying an etchant operable to etch a portion of the dielectric region; wherein the gate spacer has a first etch rate responsive to the etchant; wherein the etch stop material has a second etch rate responsive to the etchant; wherein the second etch rate is less than the first etch rate; and wherein the etch stop material is soluble responsive to an etch stop removal material selected from the group consisting of water and an acid.
11. 11 . The IC fabrication method of claim 10 , wherein: the acid comprises a weak acid; and the weak acid comprises an acid dissociation constant (Ka) at or below about 1×10 −5 . 12. The IC fabrication method of claim 10 , wherein the etch stop material further comprise a vapor pressure at or below a predetermined vapor pressure level.
12. 13 . The IC fabrication method of claim 12 , wherein the predetermined vapor pressure level is about 1 Torr.
13. 14 . The IC fabrication method of claim 10 , wherein the etch stop material further comprise a boiling point above a predetermined boiling point.
14. 15 . The IC fabrication method of claim 14 , wherein the predetermined boiling point is 1300 degrees Celsius.
15. 16 . The IC fabrication method of claim 10 , wherein the etch stop material further comprises: a vapor pressure below a predetermined vapor pressure level; and a boiling point above a predetermined boiling point.
16. 17 . The IC fabrication method of claim 16 , wherein: the predetermined vapor pressure level is 1 Torr; and the predetermined boiling point is 1300 degrees Celsius.
17. 18 . An integrated circuit (IC) fabrication method comprising: forming a transistor comprising a gate spacer and a source or drain (S/D); forming an etch stop material; forming a dielectric region over the S/D, wherein a first portion of the etch stop material is between a portion of the dielectric region and a portion of the gate spacer; and forming a S/D contact trench in the dielectric region by applying an etchant operable to etch the dielectric region; wherein the first portion of the etch stop material prevents the portion of the gate spacer from being contacted by the etchant; and wherein the etch stop material is soluble responsive to an etch stop removal material selected from the group consisting of water and an acid.
18. 19 . The IC fabrication method of claim 18 further comprising, subsequent to forming the S/D trench, removing the first portion of the etch stop material.
19. 20 . The IC fabrication method of claim 19 , wherein, subsequent to removing the first portion of the etch stop material, a second portion of the etch stop material remains in an IC formed by the IC fabrication method.
20. 21 . The IC fabrication method of claim 18 , wherein: the acid comprises a weak acid; the weak acid comprises an acid dissociation constant (Ka) at or below about 1×10 −5 ; and the etch stop material further comprise a boiling point above 1300 degrees Celsius.

Description

BACKGROUND The present disclosure relates in general to fabrication methods and resulting structures for semiconductor devices. More specifically, the present disclosure relates to fabrication methods and resulting structures for selectively incorporating into an integrated circuit (IC) an etch stop material that is robust (e.g., etch-resistant) and easily-removed. The various processes used to form a micro-chip that will be packaged into an IC fall into four (4) general categories, namely, film deposition, removal/etching, semiconductor doping and patterning/lithography. Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Removal/etching is any process that removes material from the wafer. Example removal processes include etch processes (either wet or dry), chemical-mechanical planarization (CMP), and the like. To control removal/etching operations, so-called “etch stop” layers can be included in IC fabrication processes. In general, an “etch stop” is formed from material configured to prevent specific regions of a semiconductor wafer from being unintentionally removed. SUMMARY Embodiments of the disclosure are directed to an integrated circuit (IC) that includes a transistor, a dielectric region and an etch stop material. A portion of the etch stop material is between a portion of the dielectric region and a portion of a gate spacer material of the transistor. The etch stop material is soluble responsive to an etch stop removal material selected from the group consisting of water and an acid. Embodiments of the disclosure are directed to an IC fabrication method that includes forming an etch stop material, where a portion of the etch stop material is adjacent a gate spacer of a transistor-under-fabrication (TUF). A dielectric region is formed over the portion of the etch stop material, and an etchant operable to etch a portion of the dielectric region is applied. The gate spacer has a first etch rate responsive to the etchant, the etch stop material has a second etch rate responsive to the etchant, and the second etch rate is greater than the first etch rate. The etch stop material is soluble responsive to an etch stop removal material selected from the group consisting of deionized water and an acid. Embodiments of the disclosure are directed to an IC fabrication method that includes forming a transistor including a gate spacer and a source or drain (S/D). An etch stop material is formed. A dielectric region is formed over the S/D, where a first portion of the etch stop material is between a portion of the dielectric region and a portion of the gate spacer. A S/D contact trench is formed in the dielectric region by applying an etchant operable to etch the dielectric region. The first portion of the etch stop material prevents the portion of the gate spacer from being contacted by the etchant. The etch stop material is soluble responsive to an etch stop removal material selected from the group consisting of deionized water and an acid Embodiments of the disclosure are directed to an IC fabrication method that includes forming a transistor including a gate spacer and a S/D. A layer of an etch stop material is conformally deposited. A first dielectric region is formed over the S/D, where a first portion of the layer of the etch stop material is between a portion of the first dielectric region and a portion of the gate spacer. A S/D contact trench is formed in the first dielectric region by applying an etchant operable to etch the first dielectric region. The first portion of the layer of the etch stop material prevents the portion of the gate spacer from being contacted by the etchant. An etch rate of the etch stop material responsive to the etchant is less than an etch rate of the gate spacer responsive to the etchant. The etch stop material is soluble responsive to an etch stop removal material selected from the group consisting of deionized water and an acid. Subsequent to forming the S/D trench, the first portion of the layer of the etch stop material is removed. Subsequent to removing the first portion of the layer of the etch stop material, a second portion of the layer of the etch stop material remains in a final version of the IC. Embodiments of the disclosure are directed to an IC fabrication method that includes forming a transistor that includes a gate spacer, a S/D, and a gate cap. A layer of an etch stop material is formed. A first dielectric region is formed over the S/D. A first portion of the layer of the etch stop material is between a portion of the first dielectric region and a portion of the gate spacer. A S/D contact trench is formed in the first dielectric region by applying an etchant operable to etch the first dielectric region. The first portion of the layer of the etch stop material prevents the portion of the gate spacer from being contacted by the etchant. An etch rate of the etch stop material responsive to the etchant is less than an