US-20260130164-A1 - ETCHING SYSTEM AND ETCHING METHOD

US20260130164A1US 20260130164 A1US20260130164 A1US 20260130164A1US-20260130164-A1

Abstract

The present application discloses an etching system. The etching system includes a process chamber, an image and temperature control device, and an artificial intelligence control module. The process chamber is configured to execute an etching process based on a first etching recipe on a first wafer. The image and temperature control device is configured to generate a thermal image of the first wafer during the etching process. The artificial intelligence control module is configured to determine whether the thermal image is compliant with a predetermined requirement. When the thermal image is not compliant with the predetermine requirement, the artificial intelligence control module is configured to update the first etching recipe according to the plurality of parameters so as to generate a second etching recipe.

Inventors

Tse-Yao Huang

Assignees

NANYA TECHNOLOGY CORPORATION

Dates

Publication Date: 20260507
Application Date: 20241211

Claims (17)

1 . An etching system, comprising: a process chamber, configured to execute an etching process based on a first etching recipe on a first wafer; an image and temperature control device, configured to generate a thermal image of the first wafer during the etching process; an artificial intelligence (AI) control module, configured to determine whether the thermal image is compliant with a predetermined requirement, wherein when the thermal image is not compliant with the predetermine requirement, the AI control module is configured to update the first etching recipe according to a plurality of parameters so as to generate a second etching recipe; and a measurement device, configured to monitor the plurality of parameters of the etching process and transmit the plurality of parameters to the AI control module; wherein the process chamber is further configured to execute the etching process based on the second etching recipe on a second wafer, wherein the second etching recipe is different from the first etching recipe.
2 . The etching system of claim 1 , wherein the AI control module is integrated in the process chamber.
3 . The etching system of claim 1 , wherein the process chamber comprises: an electrostatic chunk (ESC), configured to adhere the first wafer via an electroadhesion; a plurality of thermal sensors, configured to sense a plurality of temperature informations of the first wafer, respectively; and a pedestal, configured to support the ESC.
4 . The etching system of claim 3 , wherein the pedestal comprises: a channel, configured to transmit a heat transfer liquid to control a temperature of the first wafer.
5 . The etching system of claim 4 , wherein a flow rate of the heat transfer liquid is monitored in real-time, and the flow rate is transmitted to the AI control module, wherein when the thermal image is not compliant with the predetermine requirement, the AI control module updates the first etching recipe according the flow rate to generate the second etching recipe.
6 . The etching system of claim 5 , wherein when AI control module updates the first etching recipe, the AI control module is further configured to update the flow rate according to the thermal image.
7 . The etching system of claim 3 , wherein when the ESC adheres the first wafer, an air gap exists between the first wafer and the ESC, wherein a heat transfer gas is purged into the air gap, wherein a purge pressure of the heat transfer gas is monitored in real-time, and the purge pressure is transmitted to the AI control module.
8 . The etching system of claim 7 , wherein when the thermal image is not compliant with the predetermine requirement, the AI control module updates the first etching recipe according the purge pressure.
9 . The etching system of claim 8 , wherein when AI control module updates the first etching recipe, the AI control module is further configured to update the purge pressure according to the thermal image.
10 . The etching system of claim 3 , wherein image and temperature control device is configured to obtain the plurality of temperature informations so as to generate the thermal image.
11 . The etching system of claim 3 , wherein the plurality of temperature informations indicate a temperature of a plurality of regions of the first wafer, respectively.
12 . The etching system of claim 3 , wherein the ESC comprises: a dielectric body; an electrode, buried in the dielectric body; and a voltage provider, configured provide a voltage to the electrode, wherein a first charge is accumulated on the electrode due to the voltage, and a second charge is induced by the first charge and accumulated on the first wafer.
13 . The etching system of claim 3 , wherein the ESC comprises: a dielectric body; a first electrode, buried in the dielectric body; a second electrode, buried in the dielectric body and separated from the first electrode; and a voltage provider, coupled between the first electrode and the second electrode, and configured provide a voltage between the first electrode and the second electrode, wherein a first positive charge and a first negative charge are accumulated on the first electrode and the second electrode due to the voltage, respectively, wherein a second negative charge is induced by the first positive charge and accumulated on a portion of the first wafer, and a second positive charge is induced by the first negative charge and accumulated on another portion of the first wafer.
14 . An etching method, comprising: obtaining a thermal image of a first wafer; performing an etching process on the first wafer based on a first etching recipe; determining, by an artificial intelligence (AI) control module, whether the thermal image is compliant with a predetermined requirement; when the thermal image is not compliant with the predetermined requirement, updating the first etching recipe to generate a second etching recipe by the AI control module according to the thermal image; and performing the etching process on a second wafer based on the second etching recipe; wherein performing the etching process on the first wafer based on the first etching recipe comprises: sensing a plurality of temperature information of a plurality of regions of the first wafer, respectively; and generating a plasma to etch the first wafer; wherein sensing the plurality of temperature information are performed when the plasma is not generated.
15 . The etching method of claim 14 , wherein performing the etching process on the first wafer based on the first etching recipe further comprises: purging a heat transfer gas to control a temperature of the wafer; and transferring a heat transfer liquid to control the temperature of the wafer.
16 . The etching method of claim 15 , further comprising: monitoring a flow rate of the heat transfer liquid and a purging pressure of the heat transfer gas in real-time; and when the thermal image is not compliant with the predetermined requirement, updating, by the AI control module, the flow rate and the purging pressure.
17 . The etching method of claim 16 , wherein when performing the etching process on the second wafer based on the second etching recipe is performed, the heat transfer gas is purged with the purging pressure being updated, and the heat transfer liquid is transferred with the flow rate being updated.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation application of U.S. Non-Provisional application Ser. No. 18/934,443 filed Nov. 1, 2024, which is incorporated herein by reference in its entirety. TECHNICAL FIELD The present disclosure relates to an etching system and an etching method, and more particularly, to an etching system and an etching method using an artificial intelligence control module. DISCUSSION OF THE BACKGROUND Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular telephones, digital cameras, and other electronic equipment. The dimensions of semiconductor devices are continuously being scaled down to meet the increasing demand of computing ability. However, a variety of issues arise during the scaling-down process, and such issues are continuously increasing. Furthermore, the temperature variation can cause rick of wafer breaking especially to the thinner wafer or wafer having the scaling-down process. Therefore, challenges remain in achieving improved quality, yield, performance, and reliability and reduced complexity. This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes prior art to the present disclosure, and no part of this Discussion of the Background section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure. SUMMARY One aspect of the present disclosure provides an etching system. The etching system includes a process chamber, an image and temperature control device, and an artificial intelligence control module. The process chamber is configured to execute an etching process based on a first etching recipe on a first wafer. The image and temperature control device is configured to generate a thermal image of the first wafer during the etching process. The artificial intelligence control module is configured to determine whether the thermal image is compliant with a predetermined requirement. When the thermal image is not compliant with the predetermine requirement, the artificial intelligence control module is configured to update the first etching recipe according to the plurality of parameters so as to generate a second etching recipe. Another aspect of the present disclosure provides an etching method. The etching method includes: obtaining a thermal image of a first wafer; performing an etching process on the first wafer based on a first etching recipe; determining, by an artificial intelligence control module, whether the thermal image is compliant with a predetermined requirement; when the thermal image is not compliant with the predetermined requirement, updating the first etching recipe to generate a second etching recipe by the artificial intelligence control module according to the thermal image; and performing the etching process on a second wafer based on the second etching recipe. Due to the usage of artificial intelligence control module, the temperature of the wafer can be controlled more precisely and timely. As a result, the yield and/or reliability of the wafers may be improved. The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter, and form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a schematic diagram of an etching system in accordance with some embodiments of the present disclosure. FIG. 2 is a schematic diagram of a process chamber in accordance with some embodiments of the present disclosure. FIG. 3 is a schematic diagram of an electroadhesion between a wafer and an electrostatic chunk in accordance with some embodiments of the present disclosure. FIG. 4 is a schematic diagram of a process chamber in accordance with other embodimen