US-20260130178-A1 - MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

US20260130178A1US 20260130178 A1US20260130178 A1US 20260130178A1US-20260130178-A1

Abstract

A memory device, and a method of manufacturing the same, includes a stacked body in which conductive layers and interlayer insulating layers are alternately stacked in a stacking direction. The memory device also includes a chip guard enclosing a chip area of the stacked body, the chip guard penetrating through the stacked body in the stacking direction. The memory device further includes test electrodes electrically coupled to the chip guard. The test electrodes are spaced apart from each other, and at least a portion of the chip area is disposed between the test electrodes.

Inventors

Jae Ho Kim

Assignees

SK Hynix Inc.

Dates

Publication Date: 20260507
Application Date: 20250331
Priority Date: 20241107

Claims (20)

1 . A memory device, comprising: a stacked body in which conductive layers and interlayer insulating layers are alternately stacked in a stacking direction; a chip guard enclosing a chip area of the stacked body, the chip guard penetrating through the stacked body in the stacking direction; and test electrodes electrically coupled to the chip guard, wherein the test electrodes are spaced apart from each other, and at least a portion of the chip area is disposed between the test electrodes.
2 . The memory device according to claim 1 , wherein the chip guard comprises: a vertical structure penetrating through the stacked body; at least one upper line and at least one upper plug which are located over the stacked body; and at least one lower line and at least one lower plug which are located under the stacked body.
3 . The memory device according to claim 2 , wherein at least one of the test electrodes is coupled to the at least one upper line.
4 . The memory device according to claim 2 , wherein the vertical structure comprises: a plurality of pillar structures extending in the stacking direction and arranged along a first direction crossing the stacking direction.
5 . The memory device according to claim 2 , wherein the vertical structure comprises a plate extending along a first direction crossing the stacking direction.
6 . The memory device according to claim 1 , wherein the test electrodes are arranged symmetrically with respect to the center of the chip area enclosed by the chip guard.
7 . The memory device according to claim 1 , wherein: a first test electrode of the test electrodes is coupled to the chip guard, and a second test electrode of the test electrodes is coupled to the chip guard across the chip area from the first test electrode.
8 . The memory device according to claim 1 , wherein the test electrodes extend from the chip guard into the chip area.
9 . The memory device according to claim 1 , further comprising: a test circuit connected to the test electrodes, wherein the test circuit is configured to determine, using an electrical signal input to the chip guard, whether a defect has occurred in the stacked body.
10 . The memory device according to claim 9 , wherein the test circuit is configured to determine whether a defect has occurred in the stacked body using resistance gradient information obtained through the test electrodes.
11 . The memory device according to claim 1 , further comprising: a detection circuit disposed between the chip area and the chip guard.
12 . The memory device according to claim 11 , wherein the detection circuit comprises: at least one upper detection line and at least one upper detection plug which are located over the stacked body; and at least one lower detection line and at least one lower detection plug which are located under the stacked body.
13 . The memory device according to claim 11 , wherein the detection circuit does not penetrate the stacked body.
14 . The memory device according to claim 1 , further comprising: cell plugs penetrating through the stacked body in the chip area; and contacts respectively coupled to the conductive layers in the chip area.
15 . The memory device according to claim 14 , further comprising: a semiconductor layer below the stacked body, wherein the cell plugs contact the semiconductor layer.
16 . A method of manufacturing a memory device, the method comprising: forming a stacked body in which sacrificial layers and interlayer insulating layers are alternately stacked; forming first and second sets of openings passing through the stacked body; forming cell plugs filling the first set of the openings; forming a vertical structure filling the second set of the openings; replacing the sacrificial layers with conductive layers; forming a chip guard, wherein the chip guard includes the vertical structure; forming test electrodes that are electrically connected to the chip guard and to a test circuit, wherein the test circuit is configured to determine, using an electrical signal input to the chip guard through the test electrodes, whether a defect has occurred in the stacked body.
17 . The method according to claim 16 , further comprising, before the stacked body is formed, forming a lower insulating layer; and forming at least one lower line and at least one lower plug that are enclosed by the lower insulating layer.
18 . The method according to claim 17 , wherein forming the vertical structure comprises: forming the vertical structure to be coupled to the at least one lower line and the at least one lower plug.
19 . The method according to claim 16 , further comprising, before the test electrodes are formed, forming an upper insulating layer on the stacked body; and forming at least one upper line and at least one upper plug that are enclosed by the upper insulating layer.
20 . The method according to claim 16 , wherein forming the test electrodes comprises: forming the test electrodes to be spaced apart from each other, wherein the cell plugs are disposed between the test electrodes.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2024-0157182 filed on Nov. 7, 2024, in the Korean Intellectual Property Office, the entire contents of which application is incorporated herein by reference. BACKGROUND 1. Technical Field Various embodiments of the present disclosure relate to a memory device and a method of manufacturing the memory device, and more particularly, to a memory device including a memory block having a three-dimensional (3D) structure and a method of manufacturing the memory device. 2. Related Art Through a semiconductor integration process, a plurality of chip areas may be formed on a semiconductor substrate. The plurality of chip areas may be distinguished from each other by using a scribe lane area as a boundary. The chip areas are separated from each other through a cutting process, and thus a plurality of semiconductor chips may be manufactured. Each of the semiconductor chips may include a nonvolatile memory device in which stored data is retained even when supplied power is interrupted. The nonvolatile memory device may be classified as a two-dimensional (2D) structure or a three-dimensional (3D) structure according to the structure in which memory cells are arranged. The memory cells of a nonvolatile memory device having a 2D structure may be arranged in a single layer on a substrate, and the memory cells of a nonvolatile memory device having a 3D structure may be vertically stacked on a substrate. Because the degree of integration of the nonvolatile memory device having a 3D structure is higher than that of the nonvolatile memory device having a 2D structure, the number of electronic devices using the nonvolatile memory device having a 3D structure has recently increased. SUMMARY In accordance with an embodiment of the present disclosure, a memory device may include: a stacked body in which conductive layers and interlayer insulating layers are alternately stacked in a stacking direction; a chip guard enclosing a chip area of the stacked body, the chip guard penetrating through the stacked body in the stacking direction; and test electrodes electrically coupled to the chip guard. The test electrodes are spaced apart from each other, and at least a portion of the chip area is disposed between the test electrodes. In accordance with an embodiment of the present disclosure, a method of manufacturing a memory device may include: forming a stacked body in which sacrificial layers and interlayer insulating layers are alternately stacked; forming first and second sets of openings passing through the stacked body; forming cell plugs filling the first set of the openings; forming a vertical structure filling the second set of the openings; replacing the sacrificial layers with conductive layers; forming a chip guard, wherein the chip guard includes the vertical structure; forming test electrodes that are electrically connected to the chip guard and to a test circuit, wherein the test circuit is configured to determine, using an electrical signal input to the chip guard through the test electrodes, whether a defect has occurred in the stacked body. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a view illustrating the structure of a memory device according to an embodiment of the present disclosure. FIGS. 2A and 2B show views for describing a memory device including a chip guard according to the present disclosure. FIGS. 3A, 3B, and 3C show views illustrating the arrangement of test electrodes and the planar shape of a chip guard according to various embodiments of the present disclosure. FIGS. 4A and 4B show views for describing a memory device including a chip guard and a detection circuit according to the present disclosure. FIGS. 5A and 5B show views for describing a memory device including a chip guard and a memory cell array according to the present disclosure. FIGS. 6A, 6B, 6C, 6D, and 6E show views for describing a method of manufacturing a memory device including a chip guard according to the present disclosure. FIG. 7 is a diagram illustrating a memory card system to which a memory device according to the present disclosure is applied. FIG. 8 is a diagram illustrating a solid-state drive (SSD) system to which a memory device according to the present disclosure is applied. DETAILED DESCRIPTION Specific structural or functional descriptions in embodiments of the present disclosure introduced in this specification or application are provided as examples to describe embodiments according to the concept of the present disclosure. Embodiments according to the concept of the present disclosure may be practiced in various forms and should not be construed as being limited to embodiments described in the specification or application. Hereinafter, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings in which embodiments of the p