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US-20260130181-A1 - ISOLATED ACTIVE DEVICES AND METHODS FOR FORMING AND USING

US20260130181A1US 20260130181 A1US20260130181 A1US 20260130181A1US-20260130181-A1

Abstract

Methods for forming a silicon-on-insulator (SOI) substrate are disclosed. A substrate includes a sacrificial layer and a first substrate layer over the sacrificial layer. Vias are formed around a first substrate region of the first substrate layer down to the sacrificial layer. The sacrificial layer is etched away, forming a buried volume. Substrate supports connecting the first substrate region to the first substrate layer are converted into a dielectric material. The buried volume and the vias are filled with a first dielectric material, forming a buried dielectric layer and a first dielectric sidewall around the first substrate region. A second substrate layer is formed over the first substrate layer. A trench is formed around a second substrate region of the second substrate layer. The trench is filled with a second dielectric material to form a second dielectric sidewall around the second substrate region connected to the first dielectric sidewall.

Inventors

  • Kuan-Yu Chen
  • Yu-Hsing Chang
  • CHING-HSIANG HSIEH
  • Chung-Chuan Tseng

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date
20260507
Application Date
20241101

Claims (20)

  1. 1 . A method, comprising: forming a sacrificial layer within a substrate and a first substrate layer over the sacrificial layer; forming a plurality of vias around a first substrate region of the first substrate layer extending to the sacrificial layer; etching away the sacrificial layer to form a buried volume, wherein the first substrate region is connected to the first substrate layer by a plurality of substrate supports; converting the plurality of substrate supports into a dielectric material; filling the buried volume and the plurality of vias with a first dielectric material to form a buried dielectric layer and a first dielectric sidewall around the first substrate region; forming a second substrate layer over the first substrate layer; forming a trench around a second substrate region of the second substrate layer; and filling the trench with a second dielectric material to form a second dielectric sidewall around the second substrate region.
  2. 2 . The method of claim 1 , wherein the sacrificial layer and the first substrate layer are formed by: forming the sacrificial layer within an upper surface of the substrate; and depositing the first substrate layer over the upper surface of the substrate.
  3. 3 . The method of claim 1 , wherein the sacrificial layer and the first substrate layer are formed by: implanting ions within the substrate to form the sacrificial layer; wherein the first substrate layer is a layer of the substrate located above the sacrificial layer.
  4. 4 . The method of claim 1 , further comprising planarizing the second substrate layer after the second dielectric sidewall is formed.
  5. 5 . The method of claim 1 , wherein the first dielectric material is deposited by chemical vapor deposition (CVD).
  6. 6 . The method of claim 1 , wherein the sacrificial layer is etched away using a selective gas etchant.
  7. 7 . The method of claim 1 , wherein the plurality of substrate supports are converted into a dielectric material by oxidation.
  8. 8 . The method of claim 1 , wherein the first dielectric material and the second dielectric material are silicon dioxide.
  9. 9 . The method of claim 1 , wherein a depth of the second substrate region is greater than a depth of the first substrate region.
  10. 10 . The method of claim 1 , wherein a surface area of the second substrate region is less than a surface area of the first substrate region.
  11. 11 . The method of claim 1 , wherein a thickness of the second dielectric sidewall is greater than a thickness of the first dielectric sidewall.
  12. 12 . The method of claim 1 , wherein the second substrate region is not centered along its width and length over the first substrate region.
  13. 13 . The method of claim 1 , wherein the trench formed around the second substrate region extends down to the first dielectric sidewall.
  14. 14 . The method of claim 1 , wherein the formation of the trench around the second substrate region removes the first dielectric sidewall.
  15. 15 . A structure, comprising: a buried dielectric layer within a substrate; and a dielectric sidewall extending from the buried dielectric layer to an upper surface of the substrate, wherein the dielectric sidewall surrounds a first substrate region and a second substrate region above the first substrate region; wherein an area of the second substrate region is different from an area of the first substrate region.
  16. 16 . The SOI substrate of claim 15 , wherein the area of the second substrate region is less than the area of the first substrate region.
  17. 17 . The SOI substrate of claim 15 , wherein the second substrate region is not centered along its width and length over the first substrate region.
  18. 18 . The SOI substrate of claim 15 , wherein the dielectric sidewall comprises a first dielectric sidewall below a second dielectric sidewall; wherein a thickness of the first dielectric sidewall is different from a thickness of the second dielectric sidewall.
  19. 19 . A method, comprising: receiving a silicon-on-insulator (SOI) substrate comprising: a buried dielectric layer within a substrate; and a vertical dielectric sidewall extending from the buried dielectric layer to an upper surface of the substrate, wherein the vertical dielectric sidewall surrounds a first substrate region and a second substrate region above the first substrate region; wherein a surface area of the second substrate region is different from a surface area of the first substrate region; and forming source/drain electrodes in the second substrate region; forming a gate dielectric layer upon the second substrate region; and forming a gate electrode upon the gate dielectric layer.
  20. 20 . The method of claim 19 , further comprising forming isolation regions in the second substrate region.

Description

BACKGROUND Integrated circuits are formed on a semiconductor wafer. Photolithographic patterning processes use ultraviolet light to transfer a desired mask pattern to a photoresist on a semiconductor wafer. Etching processes may then be used to transfer to the pattern to a layer below the photoresist. This process is repeated multiple times with different patterns to build different conductive, resistive, and/or insulating layers on the wafer substrate and make a useful semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1A is a perspective view of a silicon-on-insulator (SOI) substrate, in accordance with some embodiments of the present disclosure. FIG. 1B is a plan view of FIG. 1A. FIG. 1C is a Y-axis cross-sectional view through line C-C of FIG. 1B. FIG. 1D is a Y-axis cross-sectional view through line D-D of FIG. 1B. FIG. 1E is an X-axis cross-sectional view through line E-E of FIG. 1B. FIG. 1F is an X-axis cross-sectional view through line F-F of FIG. 1B. FIG. 2 is a flow chart illustrating a method for making an SOI substrate, in accordance with some embodiments. FIG. 3A is a perspective view of a substrate with a sacrificial layer formed therein. FIG. 3B is a Y-axis cross-sectional view through line B-B of FIG. 3A. FIG. 4A is a perspective view of the substrate either after deposition of a substrate layer to bury the sacrificial layer, or in an alternative embodiment after ion implantation within the substrate to form the sacrificial layer. FIG. 4B is a Y-axis cross-sectional view through line B-B of FIG. 4A. FIG. 5A is a perspective view of the substrate after etching of vias through the silicon layer down to the sacrificial layer and subsequent lateral etching to remove the sacrificial layer. FIG. 5B is a Y-axis cross-sectional view through line B-B of FIG. 5A. FIG. 5C is a Y-axis cross-sectional view through line C-C of FIG. 5A. FIG. 6A is a perspective view of the substrate after oxidation of substrate supports. FIG. 6B is a Y-axis cross-sectional view through line B-B of FIG. 6A. FIG. 6C is a Y-axis cross-sectional view through line C-C of FIG. 6A. FIG. 7A is a perspective view of the substrate after formation of a buried dielectric layer in the etched areas. A first dielectric sidewall is also formed around a first substrate region. FIG. 7B is a Y-axis cross-sectional view through line B-B of FIG. 7A. FIG. 7C is a Y-axis cross-sectional view through line C-C of FIG. 7A. FIG. 8A is a perspective view of the substrate after deposition of another substrate layer over the first substrate layer. FIG. 8B is a Y-axis cross-sectional view through line B-B of FIG. 8A. FIG. 8C is a Y-axis cross-sectional view through line C-C of FIG. 8A. FIG. 9A is a perspective view of the substrate after etching to form a trench that exposes the first dielectric sidewall. The trench surrounds a second substrate region. FIG. 9B is a Y-axis cross-sectional view through line B-B of FIG. 9A. FIG. 9C is a Y-axis cross-sectional view through line C-C of FIG. 9A. FIG. 10A is a perspective view of the substrate after deposition of dielectric material into the trench to form a second dielectric sidewall and obtain the SOI substrate. FIG. 10B is a plan view of FIG. 1A. FIG. 10C is a Y-axis cross-sectional view through line C-C of FIG. 10A. FIG. 10D is a Y-axis cross-sectional view through line D-D of FIG. 10A. FIGS. 11A-11C are Y-axis cross-sectional views of different embodiments of the SOI substrate. In these figures, the thickness of the first substrate region may vary. FIGS. 12A-12C are Y-axis cross-sectional views of different embodiments of the SOI substrate. In these figures, the thickness of the second substrate region may vary. FIGS. 13A-13C are Y-axis cross-sectional views of different embodiments of the SOI substrate. In these figures, the ratio of the thickness of the second substrate region to the thickness of the first substrate region may vary. FIGS. 14A-14C are Y-axis cross-sectional views of different embodiments of the SOI substrate. In these figures, the horizontal dimensions (i.e. length and width, or Y-axis and X-axis) of the trench may vary. In addition, different vertically-oriented layers may be present within the trench. FIGS. 15A-15D are Y-axis cross-sectional views of different embodiments of the SOI substrate. In these figures, the location of the trench may be shifted along the Y-axis and/or X-axis. Again, different vertically-oriented layers may be present within the trench. FIGS. 16A-16D are Y-axis cross-sectional views of different embodiments of the SOI substrate. In these figures, the depth of the trench may vary. This may cha