US-20260130183-A1 - GATE STRUCTURES AND METHODS OF FORMING

Abstract

A method includes forming a plurality of nanostructures, the plurality of nanostructures comprising first nanostructures that are alternatingly stacked with second nanostructures and removing the first nanostructures from the plurality of nanostructures to define recesses between the second nanostructures. The method further includes after removing the first nanostructures, performing a surface repair process on the second nanostructures and forming a gate structure in the recesses around the second nanostructures. The surface repair process increases a curvature of surfaces of the second nanostructures in the recesses.

Inventors

• Hung-Yao Chen
• Shun-Siang JHAN
• Ta-Chun Ma
• Hsueh-Chang Sung
• Ming-Hua Yu
• Chii-Horng Li

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date

20260507

Application Date

20241107

Claims (20)

1. 1 . A method comprising: forming a plurality of nanostructures, the plurality of nanostructures comprising first nanostructures that are alternatingly stacked with second nanostructures; removing the first nanostructures from the plurality of nanostructures to define recesses between the second nanostructures; after removing the first nanostructures, performing a surface repair process on the second nanostructures, wherein the surface repair process increases a curvature of surfaces of the second nanostructures in the recesses; and forming a gate structure in the recesses around the second nanostructures.
2. 2 . The method of claim 1 , wherein the surface repair process comprises performing a thermal anneal process on the second nanostructures.
3. 3 . The method of claim 2 , wherein the thermal anneal process is performed a temperature in a range of 400° C. to 900° C.
4. 4 . The method of claim 2 , wherein the thermal anneal process is performed at a pressure in a range of 0.1 Torr to 300 Torr.
5. 5 . The method of claim 1 , wherein the surface repair process comprises performing a material deposition process that deposits a semiconductor material on the second nanostructures.
6. 6 . The method of claim 5 , wherein the material deposition process is performed a temperature in a range of 400° C. to 600° C. and at a pressure in a range of 0.1 Torr to 300 Torr.
7. 7 . The method of claim 5 , wherein the semiconductor material that is deposited on the second nanostructures by the material deposition process has a thickness in a range of 3 Å to 1 nm.
8. 8 . The method of claim 1 , wherein removing the first nanostructures leaves a semiconductor residue on surfaces of the second nanostructures, and wherein the method further comprises performing a cleaning process to remove the semiconductor residue before performing the surface repair process.
9. 9 . The method of claim 1 , wherein prior to removing the first nanostructures, the method further comprises: recessing the first nanostructures; and forming inner spacers on the first nanostructures, wherein the surface repair process increases a curvature of surfaces of the inner spacers in the recesses.
10. 10 . A method comprising: forming a second nanostructure between a first nanostructure and a third nanostructure, wherein the first nanostructure, the second nanostructure, and the third nanostructure are vertically stacked; removing the second nanostructure to define a recess between the first nanostructure and the third nanostructure, wherein removing the second nanostructure leaves a semiconductor residue on surfaces of the first nanostructure and the third nanostructure in the recess; performing an etching process to remove the semiconductor residue; after performing the etching process, performing a surface repair process in the recess, wherein the surface repair process increases a curvature of one or more surfaces in the recess; and forming a gate structure in the recess around the first nanostructure and the third nanostructure.
11. 11 . The method of claim 10 further comprising: recessing sidewalls the second nanostructure from sidewalls of the first nanostructure and the third nanostructure; and forming a first inner spacer and a second inner spacer on the sidewalls of the second nanostructure, wherein removing the second nanostructure further defines the recess between the first inner spacer and the second inner spacer.
12. 12 . The method of claim 11 , wherein the surface repair process increases a curvature of sidewalls of the first inner spacer and the second inner spacer.
13. 13 . The method of claim 10 , wherein the surface repair process deposits a semiconductor material on the surfaces of the first nanostructure and the third nanostructure in the recess.
14. 14 . The method of claim 10 , wherein the surface repair process is a thermal anneal process.
15. 15 . The method of claim 10 , wherein the semiconductor residue is germanium intermix residue.
16. 16 . A device comprising: a first nanostructure extending from a first source/drain region to a second source/drain region; a second nanostructure extending from the first source/drain region to the second source/drain region; and a gate structure between the first nanostructure and the second nanostructure, wherein a center region of the gate structure has a height than an edge region of the gate structure, and wherein the gate structure has a curved lateral surface at an interface between the first nanostructure and the gate structures.
17. 17 . The device of claim 16 , wherein the curved lateral surface is concave.
18. 18 . The device of claim 16 , wherein the curved lateral surface is convex.
19. 19 . The device of claim 16 , further comprising an inner spacer on a sidewall of the gate structure, wherein the gate structure has a curved sidewall at an interface between the inner spacer and the gate structure, wherein the curved sidewall is concave.
20. 20 . The device of claim 16 , further comprising an inner spacer on a sidewall of the gate structure, wherein the gate structure has a curved sidewall at an interface between the inner spacer and the gate structure, wherein the curved sidewall is convex.

Description

BACKGROUND Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. However, as the minimum features sizes are reduced, additional problems arise that should be addressed. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates an example of a nanostructure field-effect transistor (nano-FET) in a three-dimensional view, in accordance with some embodiments. FIGS. 2, 3, 4, 5A, 5B, 6A, 6B, 7A, 7B, 7C, 8A, 8B, 9A, 9B, 9C, 9D, 10A, 10B, 10C, 10D, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, 14C, 15A, 15B, 15C, 15D, 15E, 15F, 15G, 15H, 15I, 16A, 16B, 16C, 16D, 16E, 16F, 16G, 16H, 17A, 17B, 17C, 18A, 18B, 18C, 19A, 19B, and 19C illustrate varying views of intermediary steps of manufacturing a nano-FET transistor, in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In various embodiments, a stack of nanostructures is formed that includes first nanostructures alternatingly stacked with second nanostructures. The second nanostructures are subsequently replaced with a gate structure that surrounds the first nanostructures. Removing the second nanostructures may result in a residue (e.g., a semiconductor material residue, such as germanium intermix residue) remaining on surfaces of the first nanostructures, and a cleaning process (e.g., a wet cleaning) may be used to fully remove the residue and improve the electrical performance of the resulting device. However, the cleaning process may increase a surface roughness of the first nanostructures and/or over etch the first nanostructures. Various embodiments perform a surface repair process on the first nanostructures to improve the surface property and/or profile of the first nanostructures. The surface repair process may include an anneal process and/or a semiconductor re-deposition process that increases the roundness of the first nanostructures and reduces roughness of the first nanostructures. As a result, various embodiments provide reduced surface residue and improved device performance (e.g., reduced current crowding effect (CCE) at corners between the first nanostructures and the gate structures). Further, the surface repair process may be used to define a desired profile of the gate structures to achieve a desired threshold voltage. Embodiments are described below in a particular context, a die comprising nano-FETs. Various embodiments may be applied, however, to dies c