US-20260130184-A1 - DEVICE INTEGRATED WITH DEEP TRENCH ISOLATION STRUCTURE AND MANUFACTURING METHOD THEREFOR

US20260130184A1US 20260130184 A1US20260130184 A1US 20260130184A1US-20260130184-A1

Abstract

The present application relates to the field of semiconductor technologies, and in particular, to a device integrated with a deep trench isolation structure and a manufacturing method therefor. The manufacturing method may include: providing a semiconductor structure, where the semiconductor structure includes a base, a gate material layer stacked on a surface of the base, and a mask layer stacked on the gate material layer, and a functional element of a semiconductor device is formed in the base; forming a deep trench in the semiconductor structure, where the deep trench extends through the mask layer and the gate material layer, and penetrates deep into the base; filling the deep trench to form a deep trench isolation structure, where the deep trench isolation structure includes a filling structure, the filling structure is not higher than the surface of the base, and a material of the filling structure is a conductive non-metallic material; patterning and etching the gate material layer to form a gate structure; and removing the mask layer. In the present application, a manufacturing process flow of the deep trench isolation structure can be integrated into a standard process of manufacturing a gate structure of a BCD device and another device, thereby simplifying an integration process of deep trench isolation and reducing manufacturing costs.

Inventors

Binwei TIAN

Assignees

HANGZHOU FULLSEMI SEMICONDUCTOR CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20251231
Priority Date: 20250731

Claims (10)

1 . A manufacturing method for a device integrated with a deep trench isolation structure, comprising: receiving a semiconductor structure, the semiconductor structure including a base, a gate material layer on a surface of the base, and a mask layer on the gate material layer, the base including a functional element of a semiconductor device in the base; forming a deep trench in the semiconductor structure, the deep trench extending through the mask layer and the gate material layer, and extending into the base; forming a deep trench isolation structure including a filling structure in the deep trench, the filling structure being not higher than the surface of the base, and the filling structure including a conductive non-metallic material; and patterning the gate material layer to form a gate structure; and removing the mask layer.
2 . The manufacturing method according to claim 1 , further comprising: after the removing the mask layer, forming an isolation layer on the surface of the base and a surface of the deep trench isolation structure, the isolation layer covering the gate structure; forming an interlayer dielectric layer on the isolation layer; and forming a metal interconnection layer at least partially in the interlayer dielectric layer.
3 . The manufacturing method according to claim 2 , wherein the forming the metal interconnection layer at least partially in the interlayer dielectric layer includes: forming, in the interlayer dielectric layer, a plurality of contact holes extending through the interlayer dielectric layer and the isolation layer, the plurality of contact holes separately extending to the deep trench isolation structure or the gate structure, respectively; filling the plurality of contact holes with a conductive material to form a plurality of contact plug structures; and forming, on the interlayer dielectric layer, a first metal layer in contact with the contact plug structure, wherein the plurality of contact plug structures are in contact with the deep trench isolation structure and the first metal layer, or in contact with the gate structure and the first metal layer.
4 . The manufacturing method according to claim 1 , comprising forming a shallow trench isolation structure in the base, wherein the forming the deep trench includes forming the deep trench that overlaps the shallow trench isolation structure and vertically extends through the shallow trench isolation structure.
5 . The manufacturing method according to claim 4 , wherein the base has a doped buried layer located below the shallow trench isolation structure, a trench bottom of the deep trench is lower than the doped buried layer.
6 . The manufacturing method according to claim 1 , wherein the forming the deep trench in the semiconductor structure includes: forming a first blocking layer on the gate material layer; patterning the first blocking layer to expose an area of the mask layer corresponding to the deep trench; and etching the exposed area of the mask layer, an exposed area of the gate material layer, and an exposed area of the base to form the deep trench.
7 . The manufacturing method according to claim 1 , wherein the forming the deep trench isolation structure includes: forming an isolation oxide layer on a trench wall of the deep trench and on the mask layer; etching the isolation oxide layer to expose a trench bottom of the deep trench; forming a doped area through the trench bottom of the deep trench; and depositing the conductive non-metallic material in the deep trench to form the filling structure in the deep trench.
8 . The manufacturing method according to claim 7 , wherein the depositing the conductive non-metallic material to form the filling structure in the deep trench includes: depositing the conductive non-metallic material, to form a filling material layer filled in the deep trench and on the isolation oxide layer; removing a portion of the filling material layer and a portion of the isolation oxide layer on the mask layer; and etching a portion of the filling material layer and a portion of the isolation oxide layer in the deep trench until a remaining portion of the filling material layer and a remaining portion of the isolation oxide layer are not higher than the surface of the base.
9 . The manufacturing method according to claim 1 , wherein the patterning the gate material layer includes: forming a second blocking layer on a surface of the deep trench isolation structure and a first portion of the mask layer corresponding to the gate structure; etching the mask layer to remove a second portion of the mask layer not blocked by the second blocking layer; and etching a portion of the gate material layer exposed from the mask layer, and removing the second blocking layer to form the gate structure.
10 . A device integrated with a deep trench isolation structure, comprising: a base, the base including a functional element of a semiconductor device; a deep trench, located in the base; a deep trench isolation structure in the deep trench, the deep trench isolation structure including a filling structure having a conductive non-metallic material, the filling structure being not higher than a surface of the base; and a gate structure, located on the surface of the base.

Description

TECHNICAL FIELD The present application relates to the field of semiconductor technologies, and in particular, to a device integrated with a deep trench isolation structure and a manufacturing method therefor. BACKGROUND Deep trench isolation (DTI) is a critical three-dimensional isolation structure in semiconductor devices. A core function of the deep trench isolation is to implement electrical isolation between devices, making the deep trench isolation particularly suitable for device structures with high voltage, high density, and strong anti-interference requirements. SUMMARY One aspect of the present application discloses a manufacturing method for a device integrated with a deep trench isolation structure, including: providing a semiconductor structure, the semiconductor structure including a base, a gate material layer stacked on a surface of the base, and a mask layer stacked on the gate material layer, and a functional element of a semiconductor device being formed in the base; forming a deep trench in the semiconductor structure, the deep trench extending through the mask layer and the gate material layer, and penetrating deep into the base; filling the deep trench to form a deep trench isolation structure, where the deep trench isolation structure includes a filling structure, and the filling structure is not higher than the surface of the base; patterning and etching the gate material layer to form a gate structure; and removing the mask layer. In a possible implementation, after the removing the mask layer, the manufacturing method further includes: forming an isolation layer that is stacked on the surface of the base and a surface of the deep trench isolation structure and that covers the gate structure; and forming an interlayer dielectric layer on the isolation layer, and forming a metal interconnection layer based on the interlayer dielectric layer. In a possible implementation, the forming the metal interconnection layer based on the interlayer dielectric layer includes: forming, in the interlayer dielectric layer, a plurality of contact holes extending through the interlayer dielectric layer and the isolation layer, the plurality of contact holes separately extending to the deep trench isolation structure and the gate structure; filling the plurality of contact holes with conductive materials to form a plurality of contact plug structures; and forming, above the interlayer dielectric layer, a first metal layer in contact with the contact plug structure, where the plurality of contact plug structures electrically connect the deep trench isolation structure to the first metal layer, and electrically connect the gate structure to the first metal layer. In a possible implementation, a shallow trench isolation structure is formed in the base, and the deep trench is located at the shallow trench isolation structure and longitudinally extends through the shallow trench isolation structure. In a possible implementation, the base has a doped buried layer located below the shallow trench isolation structure, a trench bottom of the deep trench is lower than the doped buried layer, and the deep trench and the doped buried layer are configured to isolate adjacent device modules. In a possible implementation, the forming the deep trench in the semiconductor structure includes: forming a first blocking layer stacked on the gate material layer; performing patterning processing on the first blocking layer to expose an area of the mask layer corresponding to the deep trench; and etching the exposed area of the mask layer, an exposed area of the gate material layer, and an exposed area of the base to form the deep trench. In a possible implementation, the filling the deep trench to form the deep trench isolation structure includes: forming an isolation oxide layer that covers a trench wall of the deep trench and that is stacked on the mask layer; etching back the isolation oxide layer to expose the trench bottom of the deep trench; forming a doped area at a bottom of the trench bottom of the deep trench; and depositing a conductive non-metallic material to obtain a filling structure filled in the deep trench, to form the deep trench isolation structure. In a possible implementation, the depositing the conductive non-metallic material to obtain the filling structure filled in the deep trench, to form the deep trench isolation structure includes: depositing a conductive non-metallic material, to form a filling material layer filled in the deep trench and stacked on the isolation oxide layer; removing an area of the filling material layer and an area of the isolation oxide layer on the mask layer; and etching back an area of the filling material layer and an area of the isolation oxide layer in the deep trench until a remaining part of the filling material layer and a remaining part of the isolation oxide layer are not higher than the surface of the base, to form the deep trench isolation structure including t