US-20260130185-A1 - SEMICONDUCTOR DEVICE WITH IMPROVED BREAKDOWN VOLTAGE AND ASSOCIATED MANUFACTURING METHOD

US20260130185A1US 20260130185 A1US20260130185 A1US 20260130185A1US-20260130185-A1

Abstract

A method for forming a semiconductor device having a tub. The method includes forming a substrate of a first conductivity type that includes a tub bottom layer of the tub. The tub bottom layer is of a second conductivity type that is opposite to the first conductivity type and has a tub bottom layer peak dopant concentration plane that is substantially away from a top surface of an initial substrate layer of the substrate for a predetermined tub bottom layer buried depth that is essentially greater than 0.5 μm. The method can further include forming a plurality of tub sidewalls of the tub. The method can further include forming a high voltage transistor inside the tub.

Inventors

Ji-Hyoung Yoo
Yanjie Lian
Daping Fu

Assignees

MONOLITHIC POWER SYSTEMS, INC.

Dates

Publication Date: 20260507
Application Date: 20241105

Claims (20)

1 . A method for forming a semiconductor device, comprising: forming a substrate of a first conductivity type that includes a tub bottom layer of a tub; wherein the tub bottom layer is of a second conductivity type that is opposite to the first conductivity type; and wherein the tub bottom layer has a tub bottom layer peak dopant concentration plane that is substantially away from a top surface of an initial substrate layer of the substrate for a predetermined tub bottom layer buried depth that is essentially greater than 0.5 μm.
2 . The method of claim 1 , wherein the predetermined tub bottom layer buried depth is essentially in a range from 1 μm to 5 μm.
3 . The method of claim 1 , wherein the substrate is formed to further include a tub buried link region for each one of a plurality of tub sidewalls of the tub, and wherein the tub buried link region at least contacts with the tub bottom layer.
4 . The method of claim 3 , wherein the tub bottom layer is buried deeper than the tub buried link region in the substrate.
5 . The method of claim 3 , wherein the tub buried link region is formed in the initial substrate layer and has a tub buried link peak dopant concentration plane that is substantially away from the top surface of the initial substrate layer for a predetermined tub buried link buried depth that is smaller than the predetermined tub bottom layer buried depth.
6 . The method of claim 5 , wherein the predetermined tub bottom layer buried depth is essentially of 0.5 μm to 3.5 μm deeper than the predetermined tub buried link buried depth when inspected or measured with reference to the top surface of the initial substrate layer.
7 . The method of claim 1 , wherein forming the substrate includes: providing the initial substrate layer of the first conductivity type; implanting dopants of the second conductivity type that are suitable for and compatible with a high energy implantation process in the initial substrate layer from the top surface of the initial substrate layer to form a first buried implanted zone located at substantially an implanting-in plane with the predetermined tub bottom layer buried depth; and performing a drive in process so that the first buried implanted zone is diffused to form the tub bottom layer.
8 . The method of claim 7 , wherein forming the substrate further includes: implanting dopants of the second conductivity type that are suitable for and compatible with a low energy implantation process in the initial substrate layer from the top surface of the initial substrate layer to form a second buried implanted zone for each one of a plurality of tub sidewalls of the tub, wherein the second buried implanted zone is located at substantially an implanting-in plane with a predetermined tub buried link buried depth; and sharing the drive in process so that the second buried implanted zone is diffused to form a tub buried link region for each one of the plurality of tub sidewalls.
9 . The method of claim 1 , wherein forming the substrate further includes: forming an epitaxial layer on the initial substrate layer, wherein the epitaxial layer has a thickness in a range from 8 μm to 16 μm.
10 . The method of claim 9 , further comprising: forming a drift region of the second conductivity type for each one of a plurality of transistor cells of a high voltage transistor to be manufactured in the substrate.
11 . The method of claim 10 , further comprising: forming a RESURF region of the first conductivity type for each one of the plurality of transistor cells of the high voltage transistor in the epitaxial layer.
12 . The method of claim 11 , wherein the RESURF region of each one of the plurality of transistor cells is a buried doped region that is buried substantially at a predetermined RESURF buried depth in the epitaxial layer.
13 . The method of claim 11 , wherein the RESURF region of each one of the plurality of transistor cells is a doped region that extends from a top surface of the substrate into the epitaxial layer substantially with a predetermined RESURF depth.
14 . The method of claim 9 , further comprising: forming a tub wall linking region of the second conductivity type for each one of a plurality of tub sidewalls of the tub in the epitaxial layer, wherein the tub wall linking region is a buried doped region that is buried substantially at a predetermined tub wall linking depth in the epitaxial layer.
15 . The method of claim 14 , wherein forming the epitaxial layer includes: forming a lower portion of the epitaxial layer on the initial substrate layer; forming the tub wall linking region for each one of the plurality of tub sidewalls by a doping process in the lower portion of the epitaxial layer; and forming an upper potion of the epitaxial layer on the lower portion of the epitaxial layer.
16 . The method of claim 9 , further comprising: forming a plurality of shallow trench isolation structures at a plurality of predetermined locations in the epitaxial layer.
17 . The method of claim 3 , further comprising: forming a tub well region of the second conductivity type for each one of the plurality of tub sidewalls, wherein the tub well region extends vertically from a top surface of the substrate into the substrate until contacting with or connecting to the tub buried link region.
18 . The method of claim 14 , further comprising: forming a tub well region of the second conductivity type for each one of the plurality of tub sidewalls, wherein the tub well region extends vertically from a top surface of the substrate into the substrate until contacting with or connecting to the tub wall linking region.
19 . The method of claim 10 , further comprising: forming a body well region of the first conductivity type for each one of the plurality of transistor cells of the high voltage transistor to be manufactured in the substrate, wherein the body well region is aside the drift region.
20 . The method of claim 10 , further comprising: forming a gate region for each one of the plurality of transistor cells of the high voltage transistor; forming a body region of the first conductivity type for each one of the plurality of transistor cells of the high voltage transistor in the substrate, wherein the body region is separated from the drift region; forming a source region and a drain region of the second conductivity type for each one of the plurality of transistor cells of the high voltage transistor; forming a tub pickup region for each one of a plurality of tub sidewalls of the tub sharing the same process for forming the source region and the drain region; and forming a body contact region of the first conductivity type for each one of the plurality of transistor cells of the high voltage transistor.

Description

TECHNICAL FIELD This disclosure relates generally to semiconductor devices, and more particularly but not exclusively relates to high voltage semiconductor device and associated manufacturing method. BACKGROUND Power transistors, such as high voltage metal-oxide semiconductor (MOS) transistors are widely used in various power management applications, including used as power switching elements in power management devices for industrial and/or consumer electronic equipment. In most high current or high-power applications including notebook, servers, automotive applications etc., transistors with high voltage tolerance capacity are desired. BRIEF DESCRIPTION OF DRAWINGS The following detailed description of various embodiments of the present invention can best be understood when read in conjunction with the following drawings, in which the features are not necessarily drawn to scale but rather are drawn as to best illustrate the pertinent features. FIG. 1 illustrates a partial cross-sectional view of a semiconductor device 100 in accordance with an embodiment of the present invention. FIG. 2 illustratively shows a top plan view corresponding to the partial cross-sectional view of the semiconductor device 100 of FIG. 1. FIG. 3 illustrates a waveform diagram 300 illustrating curves of dopant concentration Cx in cm−3 versus a distance Dx in μm away from the top surface S5 of the initial substrate layer 101. FIG. 4 illustrates a partial cross-sectional view of a semiconductor device 400 in accordance with an alternative embodiment of the present invention. FIG. 5 illustrates a partial cross-sectional view of a semiconductor device 500 in accordance with an alternative embodiment of the present invention. FIG. 6 illustrates a partial cross-sectional view of a semiconductor device 600 in accordance with an alternative embodiment of the present invention. FIG. 7 illustrates a partial cross-sectional view of a semiconductor device 700 in accordance with an alternative embodiment of the present invention. FIG. 8A to FIG. 8Q illustrate partial cross-sectional views of some process stages of a method for manufacturing a semiconductor device in accordance with an embodiment of the present invention. SUMMARY There has been provided, in accordance with an embodiment of the present disclosure, a semiconductor device having a substrate of a first conductivity type, and a tub of a second conductivity type formed in the substrate, the second conductivity type being opposite to the first conductivity type. The substrate in an embodiment includes an initial substrate layer of the first conductivity type and an epitaxial layer of the first conductivity type formed on the initial substrate layer. The tub in an embodiment includes a tub bottom layer of the second conductivity type buried in the initial substrate layer. The tub bottom layer in an embodiment has a peak dopant concentration plane that is substantially away from a top surface of the initial substrate layer for a predetermined buried depth that is essentially greater than 0.5 μm. The tub in an embodiment further includes a plurality of tub sidewalls contacting or connected to the tub bottom layer, and each one of the plurality of tub sidewalls extends from a top surface of the substrate down into the substrate until at least reaches to contact or connect with the tub bottom layer. The semiconductor device in an embodiment further includes a transistor formed in a portion of the substrate located inside the tub. The transistor in an embodiment has a breakdown voltage greater than 70V up to especially over 100V. There has been provided, in accordance with an embodiment of the present disclosure, a semiconductor device. The semiconductor device has a substrate of a first conductivity type, and a tub of a second conductivity type formed in the substrate, the second conductivity type being opposite to the first conductivity type. The tub in an embodiment includes a tub bottom layer and a plurality of tub sidewalls contacting the tub bottom layer, and each of the plurality of tub sidewalls includes a tub buried link region that is a first buried layer, and the tub bottom layer includes a second buried layer disposed deeper in the substrate than the tub buried link region with reference to a top surface of the substrate. The semiconductor device in an embodiment further includes a transistor formed inside the tub. The transistor in an embodiment has a breakdown voltage greater than 70V up to especially over 100V. There has also been provided, in accordance with an embodiment of the present disclosure, a method for manufacturing a semiconductor device. The method may include forming a substrate of the first conductivity type that includes a tub bottom layer of a tub. The tub bottom layer is of a second conductivity type that is opposite to the first conductivity type; and has a tub bottom layer peak dopant concentration plane that is substantially away from a top surface of an i