US-20260130188-A1 - SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

Abstract

A semiconductor structure includes a fin structure over a substrate, a source/drain feature in the fin structure, a gate stack across the fin structure, a contact plug over the source/drain feature, a first dielectric layer over the contact plug, and a second dielectric layer over the first dielectric layer, and a via through the second dielectric layer and the first dielectric layer and on the contact plug. A width of the via varies along a vertical direction, and the via has a minimum width at a first level that is higher than a top surface of the first dielectric layer.

Inventors

• Te-Chih Hsiung
• Jyun-De Wu
• Yi-Chun Chang
• Yi-Chen Wang
• Yuan-Tien Tu

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260507

Application Date

20251229

Claims (20)

1. 1 . A semiconductor structure, comprising: a fin structure over a substrate; a source/drain feature in the fin structure; a gate stack across the fin structure, wherein the fin structure extends lengthwise along a first direction, and the gate stack extends lengthwise along a second direction that is different from the first direction; a contact plug over the source/drain feature, wherein the contact plug includes a silicide layer on the source/drain feature and a first metal bulk layer on the silicide layer and made of a different material than the silicide layer; a first dielectric layer over the contact plug; a second dielectric layer over the first dielectric layer, wherein a dielectric constant of the first dielectric layer is higher than a dielectric constant of the second dielectric layer; and a via through the second dielectric layer and the first dielectric layer and on the contact plug, wherein a width of the via varies along a vertical direction, and the via has a minimum width at a first level that is higher than a top surface of the first dielectric layer.
2. 2 . The semiconductor structure as claimed in claim 1 , wherein the via includes a lower portion lower than the first level and an upper portion higher than the first level, the lower portion of the via tapers upward, and the upper portion of the via tapers downward.
3. 3 . The semiconductor structure as claimed in claim 1 , wherein a top surface of the contact plug is higher than a top surface of the gate stack.
4. 4 . The semiconductor structure as claimed in claim 1 , wherein the via has a first width at a second level of a bottom surface of the first dielectric layer, the contact plug has a second width at the second level of the bottom surface of the first dielectric layer, and the second width is substantially equal to the first width.
5. 5 . The semiconductor structure as claimed in claim 1 , wherein the via has a first width at a second level of a bottom surface of the first dielectric layer, the contact plug has a second width at the second level of the bottom surface of the first dielectric layer, and the second width is less than the first width.
6. 6 . The semiconductor structure as claimed in claim 1 , wherein the via has a first width at a second level of a bottom surface of the first dielectric layer, the contact plug has a second width at the second level of the bottom surface of the first dielectric layer, and the second width is greater than the first width.
7. 7 . The semiconductor structure as claimed in claim 1 , wherein the via includes a lower portion lower than the first level and the lower portion of the via has a sidewall that is curved.
8. 8 . The semiconductor structure as claimed in claim 1 , further comprising: a gate spacer layer on a sidewall of the gate stack; and a mask layer over the gate stack and the gate spacer layer and under the first dielectric layer.
9. 9 . The semiconductor structure as claimed in claim 8 , wherein the contact plug is interfaced with the gate spacer layer and the mask layer.
10. 10 . A semiconductor structure, comprising: a fin structure over a substrate; an isolation structure alongside the fin structure; a gate stack over the fin structure, wherein the gate stack includes a gate dielectric layer and a gate electrode layer over the gate dielectric layer, and a dielectric constant of the gate dielectric layer is greater than a dielectric constant of the isolation structure; a gate spacer layer on a sidewall of the gate stack; a source/drain feature separated from the gate stack by the gate spacer layer; a contact plug over the source/drain feature, wherein a top surface of the contact plug is higher than a top surface of the gate stack; and a via above and electrically connected to the contact plug, wherein the via includes a lower portion and an upper portion over the lower portion, the lower portion of the via tapers upward, and the upper portion of the via tapers downward.
11. 11 . The semiconductor structure as claimed in claim 10 , wherein the via includes a barrier layer and a metal bulk layer nested within in the barrier layer.
12. 12 . The semiconductor structure as claimed in claim 10 , further comprising: a first dielectric layer surrounding the lower portion of the via; and a second dielectric layer surrounding the upper portion of the via, wherein the second dielectric layer and the first dielectric layer are made of different dielectric materials.
13. 13 . The semiconductor structure as claimed in claim 12 , wherein a dielectric constant of the first dielectric layer is higher than a dielectric constant of the second dielectric layer.
14. 14 . The semiconductor structure as claimed in claim 10 , wherein the lower portion of the via is embedded in the contact plug.
15. 15 . A method for forming a semiconductor structure, comprising: forming a transistor over a substrate; forming a contact plug on a source/drain region of the transistor; forming a first dielectric layer over the contact plug; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer with a first process pressure to form an opening; etching the first dielectric layer with a second process pressure to extend the opening into the first dielectric layer, thereby forming an enlarged opening, wherein the second process pressure is greater than the first process pressure; and forming a via in the enlarged opening.
16. 16 . The method for forming the semiconductor structure as claimed in claim 15 , wherein: the opening has a first width at a top surface of the second dielectric layer, the opening has a second width at a bottom surface of the second dielectric layer, and the first width is greater than the second width, and the enlarged opening has a third width at the bottom surface of the second dielectric layer, and the third width is greater than the second width.
17. 17 . The method for forming the semiconductor structure as claimed in claim 16 , wherein the enlarged opening has a fourth width at a level between a top surface and a bottom surface of the first dielectric layer, and the fourth width is greater than the third width.
18. 18 . The method for forming the semiconductor structure as claimed in claim 15 , wherein etching the second dielectric layer with the second process pressure comprises introducing H 2 .
19. 19 . The method for forming the semiconductor structure as claimed in claim 15 , wherein the transistor includes a plurality of nanostructures above a fin structure, and a gate stack wrapping around the plurality of nanostructures.
20. 20 . The method for forming the semiconductor structure as claimed in claim 15 , further comprising: forming a metal line on the via.

Description

PRIORITY CLAIM AND CROSS-REFERENCE This application is a Continuation Application of U.S. application Ser. No. 18/673,578, filed on May 24, 2024, entitled “FIN FIELD EFFECT TRANSISTOR (FINFET) HAVING HOURGLASS-SHAPED VIA STRUCTURE ON SOURCE/DRAIN AND METHOD FOR FORMING THE SAME,” which is a Continuation Application of U.S. application Ser. No. 17/350,974, filed on Jun. 17, 2021 (now U.S. Pat. No. 11,996,321), entitled “SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME,” which are incorporated herein by reference in its entirety. BACKGROUND Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Many integrated circuits are typically manufactured on a single semiconductor wafer, and individual dies on the wafer are singulated by sawing between the integrated circuits along a scribe line. The individual dies are typically packaged separately, in multi-chip modules, for example, or in other types of packaging. As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as the fin field effect transistor (FinFET). FinFETs are fabricated with a thin vertical “fin” (or fin structure) extending from a substrate. The channel of the FinFET is formed in this vertical fin. A gate is provided over the fin. The advantages of a FinFET may include reducing the short channel effect and providing a higher current flow. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a perspective view of a semiconductor structure, in accordance with some embodiments of the disclosure. FIGS. 2A-2G are cross-sectional views illustrating the formation of a semiconductor structure at various intermediate stages, in accordance with some embodiments of the disclosure. FIG. 2E-1 is an enlarged view of a via opening shown in FIG. 2E, in accordance with some embodiments of the disclosure. FIG. 2F-1 is an enlarged view of a via shown in FIG. 2E, in accordance with some embodiments of the disclosure. FIG. 3A is a modification of FIG. 2E-1 in accordance with some embodiments. FIG. 3B is a cross-sectional view of a semiconductor structure, in accordance with some embodiments of the disclosure. FIG. 3B-1 is an enlarged view of a via shown in FIG. 3B, in accordance with some embodiments of the disclosure. FIG. 4A is a modification of FIG. 3A in accordance with some embodiments. FIG. 4B is a cross-sectional view of a semiconductor structure, in accordance with some embodiments of the disclosure. FIG. 5A is a modification of FIG. 2E-1 in accordance with some embodiments. FIG. 5B is a cross-sectional view of a semiconductor structure, in accordance with some embodiments of the disclosure. FIG. 6A is a modification of FIG. 2E-1 in accordance with some embodiments. FIG. 6B is a cross-sectional view of a semiconductor structure, in accordance with some embodiments of the disclosure. FIG. 7A is a modification of FIG. 2E-1 in accordance with some embodiments. FIG. 7B is a cross-sectional view of a semiconductor structure, in accordance with some embodiments of the disclosure. FIG. 8 is a cross-sectional view of a semiconductor structure, in accordance with some embodiments of the disclosure. FIG. 9 is a modification of FIG. 2F-1 in accordance with some embodiments. FIG. 10 is a cross-sectional view of a semiconductor structure, in accordance with some embodiments of the disclosure. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be