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US-20260130189-A1 - DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

US20260130189A1US 20260130189 A1US20260130189 A1US 20260130189A1US-20260130189-A1

Abstract

A device structure, along with methods of forming such, are described. The device structure includes an interconnection structure disposed over a substrate, a first dielectric layer disposed over the interconnection structure, and a second dielectric layer disposed on the first dielectric layer. The second dielectric layer comprises a dielectric material having a k value greater than about 20 and a band gap less than about 5 eV. The structure further includes a third dielectric layer disposed on the second dielectric layer and a first conductive feature disposed on the third dielectric layer. The first conductive feature includes a first portion extending through the first dielectric layer, the second dielectric layer, and the third dielectric layer and a second portion disposed on the third dielectric layer.

Inventors

  • Ying-Ju Wu
  • Chia-Yueh CHOU
  • Hsiang-Ku Shen

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date
20260507
Application Date
20241104

Claims (20)

  1. 1 . A device structure, comprising: an interconnection structure disposed over a substrate; a first dielectric layer disposed over the interconnection structure; a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer comprises a dielectric material having a k value greater than about 20 and a band gap less than about 5 eV; a third dielectric layer disposed on the second dielectric layer; and a first conductive feature disposed on the third dielectric layer, wherein the first conductive feature comprises a first portion extending through the first dielectric layer, the second dielectric layer, and the third dielectric layer and a second portion disposed on the third dielectric layer.
  2. 2 . The device structure of claim 1 , wherein the second dielectric layer comprises TiO 2 , TiO, BaO, or Ta 2 O 5 .
  3. 3 . The device structure of claim 1 , wherein the second dielectric layer has a thickness ranging from about 1 angstrom to about 20 angstroms.
  4. 4 . The device structure of claim 1 , further comprising an etch stop layer disposed between the interconnection structure and the first dielectric layer, wherein the first portion of the first conductive feature extends through the etch stop layer.
  5. 5 . The device structure of claim 4 , further comprising a fourth dielectric layer, wherein the etch stop layer is disposed on the fourth dielectric layer.
  6. 6 . The device structure of claim 5 , further comprising a second conductive feature, wherein the first conductive feature is electrically connected to the second conductive feature.
  7. 7 . The device structure of claim 1 , wherein the first conductive feature is a redistribution layer.
  8. 8 . A device structure, comprising: an interconnection structure disposed over a substrate; a metal-insulator-metal (MIM) structure disposed in the interconnection structure, wherein the MIM structure comprises: a first electrode layer; a second electrode layer disposed over the first electrode layer; a first dielectric layer disposed between the first and second electrode layers; a third electrode layer disposed over the second electrode layer; and a second dielectric layer disposed between the second and third electrode layers, wherein at least one of the first and second dielectric layers comprises a dielectric material having a k value greater than about 20 and a band gap less than about 5 eV; a passivation layer disposed on the MIM structure; and a conductive feature disposed over the passivation layer, wherein the conductive feature comprises a first portion extending through the MIM structure and the passivation layer and a second portion disposed over the passivation layer.
  9. 9 . The device structure of claim 8 , wherein the first and second dielectric layers comprise different materials.
  10. 10 . The device structure of claim 9 , wherein the first dielectric layer comprises TiO 2 , TiO, BaO, or Ta 2 O 5 , and the second dielectric layer comprises an oxide of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu.
  11. 11 . The device structure of claim 10 , wherein the first dielectric layer has a first thickness, and the second dielectric layer has a second thickness greater than the first thickness.
  12. 12 . The device structure of claim 11 , wherein the k value of the first dielectric layer is greater than a k value of the second dielectric layer.
  13. 13 . The device structure of claim 11 , wherein the first thickness ranges from about 1 angstrom to about 20 angstroms.
  14. 14 . The device structure of claim 8 , wherein the first and second dielectric layers comprise the same material.
  15. 15 . The device structure of claim 8 , wherein the band gap of the dielectric material ranges from about 2 . 5 eV to about 4 . 5 eV.
  16. 16 . The device structure of claim 8 , wherein the k value of the dielectric material ranges from about 20 to about 60 .
  17. 17 . A method, comprising: depositing a first dielectric layer over an interconnection structure; depositing a second dielectric layer on the first dielectric layer, wherein the second dielectric layer comprises a dielectric material having a k value greater than about 20 and a band gap less than about 5 eV; depositing a third dielectric layer on the second dielectric layer; forming an opening in the first, second, and third dielectric layers by a plasma process; and discharging static charge accumulated on surfaces of the first and third dielectric layers by the second dielectric layer.
  18. 18 . The method of claim 17 , wherein the first and third dielectric layers are deposited by plasma processes.
  19. 19 . The method of claim 17 , further comprising depositing an etch stop layer on the interconnection structure, wherein the first dielectric layer is deposited on the etch stop layer.
  20. 20 . The method of claim 17 , further comprising forming a conductive feature in the opening, wherein the conductive feature is in contact with the second dielectric layer.

Description

BACKGROUND The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component that can be created using a fabrication process) has decreased. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIGS. 1A, 1B, 1C, and 1D are cross-sectional side views of various stages of manufacturing a device structure, in accordance with some embodiments. FIGS. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, and 2I are cross-sectional side views of various stages of manufacturing the device structure, in accordance with alternative embodiments. FIG. 3 is a cross-sectional side view of one of various stages of manufacturing the device structure, in accordance with alternative embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “on,” “top,” “upper” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Some embodiments of the disclosure are described. Additional operations can be provided before, during, and/or after the stages described in these embodiments. Some of the stages that are described can be replaced or eliminated in different embodiments. Additional features can be added to the structure. Some of the features described below can be replaced or eliminated in different embodiments. Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order. FIGS. 1A-1D are cross-sectional side views of various stages of manufacturing a device structure 100, in accordance with some embodiments. As shown in FIG. 1A, the device structure 100 includes a substrate 102. The substrate 102 may be a semiconductor substrate. In some embodiments, the substrate 102 includes a crystalline semiconductor layer on at least the surface of the substrate 102. The substrate 102 may include a crystalline semiconductor material such as, but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide (GaAsSb), and indium phosphide (InP). For example, the substrate 102 is made of Si. In some embodiments, the substrate 102 is a silicon-on-insulator (SOI) substrate, which includes an insulating layer (not shown) disposed between two silicon layers. In one aspect, the insulating layer is an oxygen-containing material, such as an oxide. In some embodiments, the substrate 102 is a wafer, such as a 200 mm wafer, a 300 mm wafer, a 450 mm wafer, or other sui