US-20260130191-A1 - SEMICONDUCTOR PACKAGE

Abstract

A semiconductor package is provided. The semiconductor package comprises a first semiconductor die including a first surface and a second surface, which are opposite to each other in a vertical direction; a second semiconductor die including a third surface and a fourth surface, which are opposite to each other in the vertical direction, the third surface facing the second surface of the first semiconductor die; a first bonding layer in contact with the first surface of the first semiconductor die; and a second bonding layer disposed between the second surface of the first semiconductor die and the third surface of the second semiconductor die, the second bonding layer being in contact with the second surface of the first semiconductor die, wherein a width of the first bonding layer in a horizontal direction is smaller than a width of the second bonding layer in the horizontal direction, wherein the width of the second bonding layer in the horizontal direction is greater than a width of the first semiconductor die in the horizontal direction.

Inventors

• Joo Hee Jang
• Ho-Jin Lee
• Jun Hong Min
• Seong Min Son
• Seung Don Lee
• Hyun Jin Lee
• Dong-Chan Lim

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20250801

Priority Date

20241105

Claims (20)

1. 1 . A semiconductor package comprising: a first semiconductor die including a first surface and a second surface, which are opposite to each other in a vertical direction; a second semiconductor die including a third surface and a fourth surface, which are opposite to each other in the vertical direction, the third surface facing the second surface of the first semiconductor die; a first bonding layer in contact with the first surface of the first semiconductor die; and a second bonding layer disposed between the second surface of the first semiconductor die and the third surface of the second semiconductor die, the second bonding layer being in contact with the second surface of the first semiconductor die, wherein a width of the first bonding layer in a horizontal direction is smaller than a width of the second bonding layer in the horizontal direction, and wherein the width of the second bonding layer in the horizontal direction is greater than a width of the first semiconductor die in the horizontal direction.
2. 2 . The semiconductor package of claim 1 , wherein the width of the first bonding layer in the horizontal direction is the same as the width of the first semiconductor die in the horizontal direction.
3. 3 . The semiconductor package of claim 1 , further comprising a filling film covering a sidewall of the first semiconductor die and being in contact with the second bonding layer.
4. 4 . The semiconductor package of claim 1 , further comprising: a third bonding layer being in contact with the third surface of the second semiconductor die and the second bonding layer; and a fourth bonding layer being in contact with the fourth surface of the second semiconductor die, wherein a width of the third bonding layer in the horizontal direction is different from a width of the fourth bonding layer in the horizontal direction.
5. 5 . The semiconductor package of claim 4 , further comprising: a first filling film covering a sidewall of the first semiconductor die and being in contact with the second bonding layer; and a second filling film covering a sidewall of the second semiconductor die and being in contact with the third bonding layer.
6. 6 . The semiconductor package of claim 4 , wherein the width of the third bonding layer in the horizontal direction is greater than the width of the fourth bonding layer in the horizontal direction.
7. 7 . The semiconductor package of claim 4 , wherein the width of the third bonding layer in the horizontal direction is greater than the width of the second semiconductor die in the horizontal direction.
8. 8 . The semiconductor package of claim 7 , wherein the width of the third bonding layer in the horizontal direction is the same as the width of the second bonding layer in the horizontal direction.
9. 9 . The semiconductor package of claim 4 , wherein the width of the fourth bonding layer in the horizontal direction is the same as the width of the first bonding layer in the horizontal direction.
10. 10 . The semiconductor package of claim 4 , wherein the width of the fourth bonding layer in the horizontal direction is the same as the width of the second semiconductor die in the horizontal direction.
11. 11 . A semiconductor package comprising: a first semiconductor die including a first surface and a second surface, which are opposite to each other in a vertical direction; a second semiconductor die including a third surface and a fourth surface, which are opposite to each other in the vertical direction, the third surface facing the second surface of the first semiconductor die; a first bonding layer in contact with the first surface of the first semiconductor die; and a second bonding layer disposed between the second surface of the first semiconductor die and the third surface of the second semiconductor die, the second bonding layer being in contact with the second surface of the first semiconductor die, wherein a width of the first bonding layer in a horizontal direction is greater than a width of the second bonding layer in the horizontal direction, and wherein the width of the second bonding layer in the horizontal direction is the same as a width of the first semiconductor die in the horizontal direction.
12. 12 . The semiconductor package of claim 11 , further comprising: a third bonding layer being in contact with the third surface of the second semiconductor die and the second bonding layer; a fourth bonding layer being in contact with the fourth surface of the second semiconductor die; a first bonding pad disposed on the first surface of the first semiconductor die, the first bonding pad passing through the first bonding layer; a second bonding pad disposed on the second surface of the first semiconductor die, the second bonding pad passing through the second bonding layer; a third bonding pad disposed on the third surface of the second semiconductor die, the third bonding pad passing through the third bonding layer; and a fourth bonding pad disposed on the fourth surface of the second semiconductor die, the fourth bonding pad passing through the fourth bonding layer, wherein the second bonding pad and the third bonding pad are in contact with each other.
13. 13 . The semiconductor package of claim 12 , further comprising: a first via disposed between the first bonding pad and the second bonding pad, the first via connecting the first bonding pad to the second bonding pad; and a second via disposed between the third bonding pad and the fourth bonding pad, the second via connecting the third bonding pad to the fourth bonding pad.
14. 14 . The semiconductor package of claim 12 , further comprising a filling film covering sidewalls of the first semiconductor die and the second semiconductor die, the filling film being in contact with the first bonding layer and the fourth bonding layer.
15. 15 . The semiconductor package of claim 11 , further comprising: a third bonding layer being in contact with the third surface of the second semiconductor die and the second bonding layer; and a fourth bonding layer being in contact with the fourth surface of the second semiconductor die, wherein a width of the third bonding layer in the horizontal direction is the same as the width of the second bonding layer in the horizontal direction.
16. 16 . The semiconductor package of claim 11 , further comprising a third bonding layer that is in contact with the third surface of the second semiconductor die and the second bonding layer, wherein the width of the first semiconductor die in the horizontal direction is the same as a width of the second semiconductor die in the horizontal direction, and wherein the width of the second bonding layer in the horizontal direction is the same as a width of the third bonding layer in the horizontal direction.
17. 17 . The semiconductor package of claim 11 , further comprising a third bonding layer being in contact with the third surface of the second semiconductor die and the second bonding layer, wherein the width of the first semiconductor die in the horizontal direction is the same as a width of the second semiconductor die in the horizontal direction, and wherein the width of the second semiconductor die in the horizontal direction is the same as a width of the third bonding layer in the horizontal direction.
18. 18 . The semiconductor package of claim 11 , further comprising a third bonding layer being in contact with the third surface of the second semiconductor die and the second bonding layer, wherein the width of the second bonding layer in the horizontal direction is the same as a width of the third bonding layer in the horizontal direction.
19. 19 . A semiconductor package comprising: a base substrate; a first semiconductor die disposed on the base substrate, the first semiconductor die including a first surface and a second surface, which are opposite to each other in a vertical direction; a second semiconductor die having a third surface and a fourth surface, which are opposite to each other in the vertical direction, the third surface facing the second surface of the first semiconductor die; a first bonding layer being in contact with the first surface of the first semiconductor die; a second bonding layer disposed between the second surface of the first semiconductor die and the third surface of the second semiconductor die, the second bonding layer being in contact with the second surface of the first semiconductor die; a third bonding layer being in contact with the third surface of the second semiconductor die and the second bonding layer; a fourth bonding layer being in contact with the fourth surface of the second semiconductor die; and a filling film covering sidewalls of the first semiconductor die and the second semiconductor die, the filling film being in contact with the first bonding layer and the fourth bonding layer, wherein a width of the first bonding layer in a horizontal direction is greater than a width of the second bonding layer in the horizontal direction, and wherein the width of the second bonding layer in the horizontal direction is the same as a width of the first semiconductor die in the horizontal direction.
20. 20 . The semiconductor package of claim 19 , further comprising: a first bonding pad disposed on the first surface of the first semiconductor die, the first bonding pad passing through the first bonding layer; a second bonding pad disposed on the second surface of the first semiconductor die, the second bonding pad passing through the second bonding layer; a third bonding pad disposed on the third surface of the second semiconductor die, the third bonding pad passing through the third bonding layer; a fourth bonding pad disposed on the fourth surface of the second semiconductor die, the fourth bonding pad passing through the fourth bonding layer; a first via disposed between the first bonding pad and the second bonding pad, the first via connecting the first bonding pad to the second bonding pad; and a second via disposed between the third bonding pad and the fourth bonding pad, the second via connecting the third bonding pad to the fourth bonding pad.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority from Korean Patent Application No. 10-2024-0155470 filed on Nov. 5, 2024 in the Korean Intellectual Property Office and all the benefits accruing therefrom under 35 U.S.C. 119, the contents of which in its entirety are herein incorporated by reference. BACKGROUND Technical Field The present disclosure relates to a semiconductor package. Description of the Related Art Many modern electronic devices use integrated chips formed on semiconductor wafers during semiconductor device manufacturing processes. Gradually, the semiconductor wafers may be stacked and bonded together to form multi-dimensional (e.g., three-dimensional) integrated chips. The multi-dimensional integrated chips have many advantages over conventional two-dimensional integrated chips, such as higher device density, faster speed, and lower power consumption. BRIEF SUMMARY An object of the present disclosure is to provide a semiconductor package capable of improving device performance and reliability. According to an aspect of the present disclosure, a semiconductor package includes a first semiconductor die including a first surface and a second surface, which are opposite to each other in a vertical direction; a second semiconductor die including a third surface and a fourth surface, which are opposite to each other in the vertical direction, the third surface facing the second surface of the first semiconductor die; a first bonding layer that in in contact with the first surface of the first semiconductor die; and a second bonding layer disposed between the second surface of the first semiconductor die and the third surface of the second semiconductor die, the second bonding layer being in contact with the second surface of the first semiconductor die, wherein a width of the first bonding layer in a horizontal direction is smaller than a width of the second bonding layer in the horizontal direction, and wherein the a width of the second bonding layer in the horizontal direction is greater than the a width of the first semiconductor die in the horizontal direction. According to an aspect of the present disclosure, a semiconductor package includes a first semiconductor die including a first surface and a second surface, which are opposite to each other in a vertical direction; a second semiconductor die including a third surface and a fourth surface, which are opposite to each other in the vertical direction, the third surface facing the second surface of the first semiconductor die; a first bonding layer that in in contact with the first surface of the first semiconductor die; and a second bonding layer disposed between the second surface of the first semiconductor die and the third surface of the second semiconductor die, the second bonding layer being in contact with the second surface of the first semiconductor die, wherein a width of the first bonding layer in a horizontal direction is greater than a width of the second bonding layer in the horizontal direction, and wherein the width of the second bonding layer in the horizontal direction is greater than a width of the first semiconductor die in the horizontal direction. According to an aspect of the present disclosure, a semiconductor package includes a base substrate; a first semiconductor die disposed on the base substrate, the first semiconductor die including a first surface and a second surface, which are opposite to each other in a vertical direction; a second semiconductor die having a third surface and a fourth surface, which are opposite to each other in the vertical direction, the third surface facing the second surface of the first semiconductor die; a first bonding layer being in contact with the first surface of the first semiconductor die; a second bonding layer disposed between the second surface of the first semiconductor die and the third surface of the second semiconductor die, the second bonding layer being in contact with the second surface of the first semiconductor die; a third bonding layer being in contact with the third surface of the second semiconductor die and the second bonding layer; a fourth bonding layer being in contact with the fourth surface of the second semiconductor die; and a filling film covering sidewalls of the first semiconductor die and the second semiconductor die and, the filling film being in contact with the first bonding layer and the fourth bonding layer, wherein a width of the first bonding layer in a horizontal direction is greater than a width of the second bonding layer in the horizontal direction, and wherein the width of the second bonding layer in the horizontal direction is the same as a width of the first semiconductor die in the horizontal direction. According to an aspect of the present disclosure, a method of manufacturing a semiconductor package includes bonding a first semiconductor die to a first substrate using a first bonding layer that is on a first s