US-20260130193-A1 - SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

US20260130193A1US 20260130193 A1US20260130193 A1US 20260130193A1US-20260130193-A1

Abstract

A semiconductor chip and a semiconductor package are disclosed. The semiconductor chip includes a device layer having a semiconductor device disposed on a front side of a substrate, and a first through via extending in a first direction intersecting the front side of the substrate and penetrating the substrate and at least a portion of the device layer. The first through via includes a first front side part that penetrates the front side of the substrate and at least a portion of the device layer, and a first back side part that is located in the substrate, connected to the first front side part, and positioned closer to a back side of the substrate than the first front side part. A width of the first back side part is greater than a width of the first front side part, thereby alleviating electrical resistance.

Inventors

Hyunsoo Chung

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20251006
Priority Date: 20241106

Claims (20)

1 . A semiconductor chip comprising: a device layer comprising a semiconductor device disposed on a front side of a substrate; and a first through via extending in a first direction intersecting the front side of the substrate and penetrating the substrate and at least a portion of the device layer, wherein the first through via comprises: a first front side part penetrating the front side of the substrate and penetrating at least the portion of the device layer; and a first back side part disposed in the substrate, connected to the first front side part and placed closer to a back side of the substrate than the first front side part, wherein the first back side part comprises a width that is greater than a width of the first front side part.
2 . The semiconductor chip of claim 1 , further comprising a first via insulation film surrounding the first through via, wherein the first via insulation film comprises: a first front side insulation film surrounding the first front side part; and a first back side insulation film surrounding the first back side part, wherein a thickness of the first front side insulation film is less than a thickness of the first back side insulation film.
3 . The semiconductor chip of claim 2 , wherein permittivity of the first front side insulation film is greater than permittivity of the first back side insulation film.
4 . The semiconductor chip of claim 2 , wherein the first front side insulation film surrounds at least a portion of the first front side part that does not overlap with the first back side part in a second direction intersecting the first direction.
5 . The semiconductor chip of claim 1 , wherein the first front side part comprises: a first connection part that is inserted into the first back side part; and a first extension part that does not overlap with the first back side part in a second direction intersecting the first direction.
6 . The semiconductor chip of claim 1 , wherein a plurality of first through vias are disposed in a second direction intersecting the first direction.
7 . The semiconductor chip of claim 1 , wherein each of the first front side part and the first back side part comprises a multi-layered film.
8 . The semiconductor chip of claim 1 , wherein the device layer further comprises a wiring layer connected to the first through via.
9 . The semiconductor chip of claim 8 , further comprising: a back side connecting pad that is connected to the first through via and placed on the back side of the substrate; and a front side connecting pad that is connected to the wiring layer and placed on the front side of the substrate.
10 . The semiconductor chip of claim 1 , wherein the first front side part comprises a width that decreases as the first front side part approaches the first back side part.
11 . The semiconductor chip of claim 1 , wherein the first back side part comprises a width that decreases as the first back side part approaches the first front side part.
12 . A semiconductor chip comprising: a device layer comprising a semiconductor device disposed on a front side of a substrate; a first through via extending in a first direction intersecting the front side of the substrate and penetrating the substrate and at least a portion of the device layer; and a second through via that is spaced apart from the first through via in a second direction intersecting the first direction, and penetrating the substrate and at least an other portion of the device layer, wherein the first through via comprises: a first front side part penetrating the front side of the substrate and penetrating at least the portion of the device layer; and a first back side part that disposed in the substrate, connected to the first front side part and placed closer to a back side of the substrate compared to the first front side part, and wherein the second through via comprises: a second front side part penetrating the front side of the substrate and penetrating at least the other portion of the device layer; and a second back side part that disposed in the substrate, connected to the second front side part, and placed closer to the back side of the substrate compared to the second front side part, wherein the first side part comprises a width that is greater than a width of the second back side part.
13 . The semiconductor chip of claim 12 , wherein the width of the first back side part is greater than the width of the first front side part, and wherein the width of the second back side part is greater than the width of the second front side part.
14 . The semiconductor chip of claim 12 , wherein the first front side part comprises a first end part disposed in the first back side part, wherein the second front side part comprises a second end part disposed in the second back side part, and wherein a distance between the back side of the substrate and the first end part in the first direction is different from a distance between the back side of the substrate and the second end part in the first direction.
15 . The semiconductor chip of claim 12 , wherein the first front side part comprises: a first connection part that is inserted into the first back side part; and a first extension part that does not overlap with the first back side part in the second direction, and wherein the second front side part comprises: a second connection part that is inserted into the second back side part; and a second extension part that does not overlap with the second back side part in the second direction.
16 . The semiconductor chip of claim 15 , wherein a length of the first connection part in the first direction is different from a length of the second connection part in the first direction.
17 . The semiconductor chip of claim 12 , wherein, based on the back side of the substrate, a depth of a first surface of the first back side part facing the device layer and a depth of a second surface of the second back side part facing the device layer are different from each other.
18 . The semiconductor chip of claim 12 , wherein the first front side part comprises a width that is equal to or greater than a width of the second front side part.
19 . The semiconductor chip of claim 12 , wherein, a power signal is transmitted through the first through via, and an input/output (I/O) signal is transmitted through the second through via.
20 . A semiconductor package comprising: a package die; and a plurality of semiconductor chips that are stacked in a first direction intersecting the package die, wherein each of the plurality of semiconductor chips comprises: a device layer comprising a semiconductor device placed on a front side of a substrate; a first through via extending in the first direction and penetrating the substrate and at least a portion of the device layer; and a second through via that is spaced apart from the first through via in a second direction intersecting the first direction, and penetrating the substrate and at least an other portion of the device layer, wherein the first through via comprises: a first front side part penetrating the front side of the substrate and penetrating at least the portion of the device layer; and a first back side part disposed in the substrate, connected to the first front side part and placed closer to a back side of the substrate compared to the first front side part, wherein the second through via comprises: a second front side part penetrating the front side of the substrate and penetrating at least the other portion of the device layer; and a second back side part disposed in the substrate, connected to the second front side part, and placed closer to the back side of the substrate compared to the second front side part, wherein a maximum width of the first back side part is greater than a maximum width of the second back side part, wherein a plurality of the first through vias of the plurality of semiconductor chips overlap each other in the first direction, and wherein a plurality of the second through vias of the plurality of semiconductor chips overlap each other in the first direction.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the benefit of Korean Patent Application No. 10-2024-0156279, filed on Nov. 6, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND 1. Field of the Invention Example embodiments relate to a semiconductor chip and a semiconductor package including the same. 2. Description of the Related Art Due to the development of the electronics industry, the demand for high-performance, high-speed, and miniaturized electronic components is increasing. In response to this trend, a method of stacking and mounting multiple semiconductor chips on a single package wiring structure and/or a method of stacking packages on top of packages can be used. For example, a package-in-package (PIP) type semiconductor package or a package-on-package (POP) type semiconductor package can be used. Meanwhile, when a through silicon via (TSV) is used to penetrate a semiconductor chip, due to the high integration of semiconductor chips, there are limits in forming TSVs. SUMMARY An aspect provides a semiconductor chip and a semiconductor package in which the electrical resistance is reduced. An aspect provides a semiconductor chip and a semiconductor package in which manufacturing processes are improved. The technical tasks to be achieved by the present example embodiments are not limited to the technical tasks described above, and other technical tasks may be inferred from the following example embodiments by those skilled in the art. According to an aspect, there is provided a semiconductor chip including a device layer including a semiconductor device placed on a front side of a substrate and a first through via extending in a first direction intersecting the front side of the substrate and penetrating the substrate and at least a portion of the device layer, wherein the first through via includes a first front side part penetrating the front side of the substrate and penetrating at least a portion of the device layer, and a first back side part that is placed in the substrate, connected to the first front side part and placed closer to a back side of the substrate than the first front side part, wherein the first back side part include a width that is greater than a width of the first front side part. According to an aspect, there is provided a semiconductor chip including a device layer including a semiconductor device placed on a front side of a substrate, a first through via extending in a first direction intersecting the front side of the substrate and penetrating the substrate and at least a portion of the device layer, and a second through via that is spaced apart from the first through via in a second direction intersecting the first direction, and penetrating the substrate and at least a portion of the device layer, wherein the first through via includes a first front side part penetrating the front side of the substrate and penetrating at least a portion of the device layer, and a first back side part that is placed in the substrate, connected to the first front side part and placed closer to a back side of the substrate than the first front side part, and the second through via includes a second front side part penetrating the front side of the substrate and penetrating at least a portion of the device layer, and a second back side part that is placed in the substrate, connected to the second front side part, and placed closer to the back side of the substrate than the second front side part, wherein the first side part includes a width that is greater than a width of the second back side part. According to an aspect, there is provided a semiconductor package including a package die and a plurality of semiconductor chips that are stacked in a first direction intersecting the package die, wherein each of the plurality of semiconductor chips includes a device layer including a semiconductor device placed on a front side of a substrate, a first through via extending in a first direction and penetrating the substrate and at least a portion of the device layer, and a second through via that is spaced apart from the first through via in a second direction intersecting the first direction, and penetrating the substrate and at least a portion of the device layer, wherein the first through via includes a first front side part penetrating the front side of the substrate and penetrating at least a portion of the device layer and a first back side part that is placed in the substrate, connected to the first front side part and placed closer to a back side of the substrate than the first front side part, and the second through via includes a second front side part penetrating the front side of the substrate and penetrating at least a portion of the device layer, a second back side part that is placed in the substrate, connected to the second front side part, and placed closer to the back side of th