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US-20260130194-A1 - SEMICONDUCTOR PACKAGES INCLUDING DIRECTLY BONDED PADS

US20260130194A1US 20260130194 A1US20260130194 A1US 20260130194A1US-20260130194-A1

Abstract

A semiconductor package comprises: a first substrate; a first pad on a top surface of the first substrate; a first conductive pattern on a bottom surface of the first pad; and a semiconductor chip on the top surface of the first substrate, wherein the semiconductor chip comprises: a semiconductor substrate; an interconnection layer on a bottom surface of the semiconductor substrate, the interconnection layer comprising an interconnection pattern; and a bonding pad on a bottom surface of the interconnection pattern, wherein the bonding pad is directly bonded to the first pad, wherein a width of the interconnection pattern is larger than a width of the bonding pad, wherein a width of the first conductive pattern is smaller than a width of the first pad, and wherein the interconnection pattern and the bonding pad comprise different materials.

Inventors

  • Minki Kim
  • Seungduk Baek

Assignees

  • SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date
20260507
Application Date
20251219
Priority Date
20211125

Claims (20)

  1. 1 .- 20 . (canceled)
  2. 21 . A semiconductor package, comprising: a first substrate; a first pad on a top surface of the first substrate; a first conductive pattern on a bottom surface of the first pad; and a semiconductor chip on the top surface of the first substrate, wherein the semiconductor chip comprises: a semiconductor substrate; an interconnection layer on a bottom surface of the semiconductor substrate, the interconnection layer comprising an interconnection pattern; and a bonding pad on a bottom surface of the interconnection pattern, wherein the bonding pad is directly bonded to the first pad, wherein a width of the interconnection pattern is larger than a width of the bonding pad, wherein a width of the first conductive pattern is smaller than a width of the first pad, and wherein the interconnection pattern and the bonding pad comprise different materials.
  3. 22 . The semiconductor package of claim 21 , wherein the interconnection pattern comprises aluminum, and wherein the bonding pad comprises copper.
  4. 23 . The semiconductor package of claim 21 , wherein a width of the bottom surface of the interconnection pattern is smaller than a width of a top surface of the interconnection pattern.
  5. 24 . The semiconductor package of claim 21 , wherein a width of a bottom surface of the bonding pad is larger than a width of a top surface of the bonding pad.
  6. 25 . The semiconductor package of claim 21 , wherein a width of the bottom surface of the first pad is smaller than a width of a top surface of the first pad.
  7. 26 . The semiconductor package of claim 21 , wherein the width of the first pad is larger than the width of the bonding pad.
  8. 27 . The semiconductor package of claim 21 , wherein the width of the interconnection pattern is larger than the width of the first pad.
  9. 28 . The semiconductor package of claim 21 , wherein a thickness of the interconnection pattern is 0.5 to 1.5 times a thickness of the bonding pad.
  10. 29 . The semiconductor package of claim 21 , wherein a thermal expansion coefficient of the interconnection pattern is greater than a thermal expansion coefficient of the bonding pad.
  11. 30 . A semiconductor package, comprising: a first substrate; a first pad on a top surface of the first substrate; a first conductive pattern on a bottom surface of the first pad; and a semiconductor chip on the top surface of the first substrate, wherein the semiconductor chip comprises: a semiconductor substrate; an interconnection layer on a bottom surface of the semiconductor substrate; and a bonding pad connected to the interconnection layer, wherein the interconnection layer comprises: an interconnection pattern on the bonding pad; and an interconnection structure comprising an interconnection line and a via on the interconnection pattern, and wherein a thickness of the interconnection pattern is larger than a thickness of the interconnection line.
  12. 31 . The semiconductor package of claim 30 , wherein the semiconductor further comprises an integrated circuit, and wherein the integrated circuit is electrically connected to the interconnection structure.
  13. 32 . The semiconductor package of claim 30 , wherein the interconnection pattern and the bonding pad comprise different materials.
  14. 33 . The semiconductor package of claim 32 , wherein a thermal expansion coefficient of the interconnection pattern is greater than a thermal expansion coefficient of the bonding pad.
  15. 34 . The semiconductor package of claim 30 , wherein a width of a bottom surface of the interconnection pattern is smaller than a width of a top surface of the interconnection pattern, and wherein a width of a bottom surface of the bonding pad is larger than a width of a top surface of the bonding pad.
  16. 35 . The semiconductor package of claim 30 , wherein a width of the first conductive pattern is smaller than a width of the first pad.
  17. 36 . The semiconductor package of claim 30 , wherein a thickness of the interconnection pattern is 0.5 to 1.5 times a thickness of the bonding pad.
  18. 37 . A semiconductor package, comprising: a first semiconductor chip; and a second semiconductor chip on a top surface of the first semiconductor chip, wherein the first semiconductor chip comprises: a first semiconductor substrate; a first integrated circuit on a bottom surface of the first semiconductor substrate; a first interconnection layer on the bottom surface of the first semiconductor substrate, the first interconnection layer comprising a first interconnection pattern and a first interconnection structure; a back-side insulating layer on a top surface of the first semiconductor substrate; a first penetration via in the first semiconductor substrate and electrically connected to the first interconnection structure; and a first bonding pad on a top surface of the first penetration via and in the back-side insulating layer and coupled to the first penetration via, wherein the first interconnection structure comprises a first interconnection line and a first via that are electrically connected to the first integrated circuit, wherein the second semiconductor chip comprises: a second semiconductor substrate; a second integrated circuit on a bottom surface of the second semiconductor substrate; a second interconnection layer on the bottom surface of the second semiconductor substrate, the second interconnection layer comprising a second interconnection structure and a second interconnection pattern; and a second bonding pad on a bottom surface of the second interconnection pattern, wherein the second interconnection structure comprises a second interconnection line and a second via that are electrically connected to the second integrated circuit, wherein a thickness of the first interconnection pattern is larger than a thickness of the first interconnection line, and wherein a thickness of the second interconnection pattern is larger than a thickness of the second interconnection line.
  19. 38 . The semiconductor package of claim 37 , wherein the second bonding pad is directly bonded to the first bonding pad.
  20. 39 . The semiconductor package of claim 37 , wherein the second interconnection pattern comprises aluminum, and wherein the first bonding pad and the second bonding pad comprise copper.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0164691, filed on Nov. 25, 2021, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference. BACKGROUND OF THE INVENTION The present disclosure relates to a semiconductor package, and in particular, to a semiconductor package including bonding pads, which are directly bonded to each other. A semiconductor package is configured to use a semiconductor chip as a part of an electronic product. In general, the semiconductor package may include a printed circuit board (PCB) and a semiconductor chip, which is mounted on the PCB and is electrically connected to the PCB using bonding wires or bumps. With development of the electronic industry, many studies are being conducted to improve reliability and durability of the semiconductor package. SUMMARY An embodiment of the inventive concept provides a semiconductor package with improved reliability, durability, and electrical characteristics. According to an embodiment of the inventive concept, a semiconductor package may include a first semiconductor chip and a second semiconductor chip on a top surface of the first semiconductor chip. The first semiconductor chip may include a first semiconductor substrate, a first bonding pad on a top surface of the first semiconductor substrate, and a first penetration via on a bottom surface of the first bonding pad and penetrating the first semiconductor substrate. The second semiconductor chip may include a second semiconductor substrate, a second interconnection pattern on a bottom surface of the second semiconductor substrate, and a second bonding pad on a bottom surface of the second interconnection pattern and coupled to the second interconnection pattern. The second bonding pad may be directly bonded to the first bonding pad. A width of the first penetration via may be smaller than a width of the first bonding pad, and a width of the second interconnection pattern may be larger than a width of the second bonding pad. According to an embodiment of the inventive concept, a semiconductor package may include a first substrate, a first pad on a top surface of the first substrate, a first conductive pattern in contact with a bottom surface of the first pad, and a semiconductor chip on the top surface of the first substrate. The semiconductor chip may include a semiconductor substrate, an interconnection layer on a bottom surface of the semiconductor substrate, the interconnection layer including an interconnection pattern, and a bonding pad coupled to a bottom surface of the interconnection pattern. The bonding pad may be directly bonded to the first pad. A width of the interconnection pattern may be larger than a width of the bonding pad, and a width of the first conductive pattern may be smaller than a width of the first pad. According to an embodiment of the inventive concept, a semiconductor package may include a first semiconductor chip and a second semiconductor chip on a top surface of the first semiconductor chip. The first semiconductor chip may include a first semiconductor substrate, first integrated circuits on a bottom surface of the first semiconductor substrate, a first interconnection layer on the bottom surface of the first semiconductor substrate, the first interconnection layer including a first insulating layer and a first interconnection structure, a first back-side insulating layer on a top surface of the first semiconductor substrate, a first penetration via in the first semiconductor substrate and electrically connected to the first interconnection structure, and a first bonding pad on a top surface of the first penetration via and in the first back-side insulating layer and coupled to the first penetration via. The second semiconductor chip may include a second semiconductor substrate, second integrated circuits on a bottom surface of the second semiconductor substrate, a second interconnection layer on the bottom surface of the second semiconductor substrate, the second interconnection layer including a second insulating layer, a second interconnection structure, and a second interconnection pattern, and a second bonding pad in contact with a bottom surface of the second interconnection pattern. The second bonding pad may be directly bonded to the first bonding pad, and the second insulating layer may be directly bonded to the first back-side insulating layer. A width of the bottom surface of the second interconnection pattern may be larger than a width of a bottom surface of the second bonding pad, and a width of a top surface of the first bonding pad may be larger than a width of the first penetration via. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a diagram illustrating a semiconductor package according to an embodiment of the inventive concept. FIG. 1B is a diagram illustrating a first