US-20260130195-A1 - SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

Abstract

An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature having a two-dimensional material layer, a second conductive feature disposed over the first conductive feature, and a dielectric material disposed adjacent the first and second conductive features. The dielectric material extends from a level of a bottom of the first conductive feature to a level of a top of the second conductive feature.

Inventors

• Yu-Chen Chan
• Shu-Wei LI
• Shin-Yi Yang
• Ming-Han Lee
• Shau-Lin Shue

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260507

Application Date

20251230

Claims (20)

1. 1 . An interconnection structure, comprising: a first conductive feature comprising a first two-dimensional material layer; a second conductive feature comprising a second two-dimensional material layer, wherein the second conductive feature fills an opening in the first conductive feature in a cross-section, wherein at a topmost surface of the first conductive feature, the second conductive feature extends from one side of the opening to the other side of the opening; and a dielectric material disposed adjacent the first and second conductive features.
2. 2 . The interconnection structure of claim 1 , wherein the first two-dimensional material layer is formed vertically.
3. 3 . The interconnection structure of claim 2 , wherein the second two-dimensional material layer is formed vertically.
4. 4 . The interconnection structure of claim 1 , wherein the first two-dimensional material layer is formed horizontally.
5. 5 . The interconnection structure of claim 2 , wherein the second two-dimensional material layer is formed horizontally.
6. 6 . The interconnection structure of claim 1 , wherein the first two-dimensional material layer comprises a plurality of graphene layers, a plurality of hexagonal-BN layers, or a plurality of transition metal dichalcogenide layers.
7. 7 . The interconnection structure of claim 6 , wherein the second two-dimensional material layer comprises a plurality of graphene layers, a plurality of hexagonal-BN layers, or a plurality of transition metal dichalcogenide layers.
8. 8 . The interconnection structure of claim 1 , further comprising first and second conductive layers, wherein the first conductive feature is disposed between the first and second conductive layers.
9. 9 . A method, comprising: depositing a first two-dimensional material layer over a dielectric layer; forming a first opening in the first two-dimensional material layer; depositing a dielectric material in the first opening and over the first two-dimensional material layer; forming a second opening in the dielectric material and the first two-dimensional material layer; and depositing a second two-dimensional material layer in the second opening, wherein the second two-dimensional material layer is electrically connected to the first two-dimensional material layer.
10. 10 . The method of claim 9 , wherein layers of the first and second two-dimensional material layers are formed horizontally.
11. 11 . The method of claim 9 , wherein layers of the first and second two-dimensional material layers are formed vertically.
12. 12 . The method of claim 9 , further comprising depositing a first conductive layer on the dielectric layer, wherein the first two-dimensional material layer is deposited on the first conductive layer.
13. 13 . The method of claim 12 , further comprising depositing a second conductive layer on the first two-dimensional material layer.
14. 14 . The method of claim 13 , further comprising selectively forming a barrier layer on the first and second conductive layers.
15. 15 . The method of claim 14 , wherein the second opening is formed in the second conductive layer and the barrier layer.
16. 16 . The method of claim 14 , wherein the second two-dimensional material layer extends through the barrier layer, the second two-dimensional material layer, and the first two-dimensional material layer.
17. 17 . An interconnection structure, comprising: a first conductive feature comprising a first two-dimensional material layer formed vertically; a second conductive feature comprising a second two-dimensional material layer formed vertically, wherein a portion of the second conductive feature is disposed in the first conductive feature; and a dielectric material disposed adjacent the first and second conductive features.
18. 18 . The interconnection structure of claim 17 , further comprising first and second conductive layers, wherein the first conductive feature is disposed between the first and second conductive layers.
19. 19 . The interconnection structure of claim 18 , further comprising a barrier layer disposed between the first conductive layer and the dielectric material and between the second conductive layer and the dielectric material.
20. 20 . The interconnection structure of claim 19 , wherein the second conductive feature extends through the first conductive feature.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a divisional application of U.S. patent application Ser. No. 18/143,818 filed May 5, 2023, which is a continuation application of U.S. patent application Ser. No. 17/184,942 filed Feb. 25, 2021, both of which are incorporated by reference in their entirety. BACKGROUND As the semiconductor industry introduces new generations of integrated circuits (IC) having higher performance and more functionality, the density of the elements forming the ICs increases, while the dimensions, sizes and spacing between components or elements are reduced. In the past, such reductions were limited only by the ability to define the structures photo-lithographically, device geometries having smaller dimensions created new limiting factors. For example, with the dimensions of the metallic conductive features in back-end-of-line (BEOL) interconnect getting smaller, sheet resistance and contact resistance increase. Therefore, improved conductive features are needed. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a cross-sectional side view of the stage of manufacturing the semiconductor device structure, in accordance with some embodiments. FIG. 2A-2E are cross-sectional side views of various stages of manufacturing an interconnection structure, in accordance with some embodiments. FIG. 3A-3D are cross-sectional side views of various stages of manufacturing the interconnection structure, in accordance with alternative embodiments. FIG. 4A-4D are cross-sectional side views of various stages of manufacturing the interconnection structure, in accordance with alternative embodiments. FIG. 5A-5D are cross-sectional side views of various stages of manufacturing the interconnection structure, in accordance with alternative embodiments. FIG. 6A-6D are cross-sectional side views of various stages of manufacturing the interconnection structure, in accordance with alternative embodiments. FIG. 7A-7C are cross-sectional side views of various stages of manufacturing the interconnection structure, in accordance with alternative embodiments. FIG. 8A-8C are cross-sectional side views of various stages of manufacturing the interconnection structure, in accordance with alternative embodiments. FIG. 9A-9D are cross-sectional side views of various stages of manufacturing the interconnection structure, in accordance with alternative embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “on,” “top,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. FIG. 1 illustrates a stage of manufacturing a semiconductor device structure 100. As shown in FIG. 1, the semiconductor device structure 100 includes a substrate 102 having substrate portions 104 extending therefrom and source/drain (S/D) epitaxial features 106 disposed over the substrate portions 104. The substrate 102 may be a semiconductor substrate, such as a bulk silicon substrate. In some embodiments, the substrate 102 may be an elementary semiconductor, such as silicon or germanium in a crystalline structure; a compound semiconductor, such as silicon germanium, silicon carbide, galliu