US-20260130196-A1 - SEMICONDUCTOR PACKAGE

Abstract

A semiconductor package includes: a first semiconductor chip including a plurality of first through-electrodes and a plurality of first shared electrodes, wherein the first through-electrodes are arranged in a first direction, wherein the plurality of first shared electrodes are spaced apart from the plurality of first through-electrodes in a second direction, intersecting the first direction, and are electrically connected to the plurality of first through-electrodes, respectively; and a second semiconductor chip including a plurality of second through-electrodes and a plurality of second shared electrodes, wherein the plurality of second through-electrodes are disposed on the first semiconductor chip and are arranged in the first direction, wherein the plurality of second shared electrodes are spaced apart from the plurality of second through-electrodes in the second direction and are electrically connected to the plurality of second through-electrodes, respectively.

Inventors

• Taeyoung Lee

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20251231

Priority Date

20220719

Claims (20)

1. 1 . A semiconductor package comprising: a plurality of semiconductor chips each including a semiconductor substrate, a through-electrode, and a shared electrode, wherein the semiconductor substrate has a front surface and a back surface opposing each other, wherein the through-electrode penetrates through the semiconductor substrate, wherein the shared electrode penetrates through the semiconductor substrate and is electrically connected to the through-electrode, wherein the plurality of semiconductor chips are stacked in a vertical direction perpendicular to the front surface or the back surface, wherein at least one of the through-electrode or the shared electrode of one of the plurality of semiconductor chips overlaps, in the vertical direction, with one of the through-electrode and the shared electrode of another one of the plurality of semiconductor chips, wherein the through-electrode and the shared electrode are symmetrically arranged with respect to a point at which a first axis and a second axis intersect each other, wherein the first axis extends in a first direction perpendicular to the vertical direction, and wherein the second axis extends in a second direction perpendicular to the vertical direction.
2. 2 . The semiconductor package of claim 1 , wherein the through-electrode and the shared electrode are electrically connected to each other.
3. 3 . The semiconductor package of claim 1 , wherein the first axis passes between the through-electrode and the shared electrode.
4. 4 . The semiconductor package of claim 1 , wherein the second axis passes through a center of the semiconductor chip.
5. 5 . The semiconductor package of claim 1 , wherein the first direction intersects the second direction.
6. 6 . The semiconductor package of claim 1 , wherein the one semiconductor chip and the other semiconductor chip are stacked such that centers thereof overlap each other in the vertical direction.
7. 7 . The semiconductor package of claim 6 , wherein the through-electrode of the one semiconductor chip overlaps the through-electrode of the other semiconductor chip in the vertical direction, and the shared electrode of the one semiconductor chip overlaps the shared electrode of the other semiconductor chip in the vertical direction.
8. 8 . The semiconductor package of claim 1 , wherein the one semiconductor chip and the other semiconductor chip are stacked such that centers thereof are shifted from each other in the second direction.
9. 9 . The semiconductor package of claim 8 , wherein the through-electrode of the one semiconductor chip overlaps the shared electrode of the other semiconductor chip in the vertical direction, or the shared electrode of the one semiconductor chip overlaps the through-electrode of the other semiconductor chip, adjacent thereto in the vertical direction.
10. 10 . A semiconductor package comprising: a plurality of semiconductor chips including a semiconductor substrate, a through-electrode, and a shared electrode, wherein the semiconductor substrate has a front surface and a back surface opposing each other, wherein the through-electrode penetrates through the semiconductor substrate, wherein the shared electrode penetrates through the semiconductor substrate and is electrically connected to the through-electrode, wherein the plurality of semiconductor chips are stacked in a vertical direction perpendicular to the front surface or the back surface, wherein at least one of the through-electrode or the shared electrode of a first semiconductor chip of the plurality of semiconductor chips overlaps with at least one of the through-electrode or the shared electrode of a second semiconductor chip of the plurality of semiconductor chips adjacent in the vertical direction, wherein the through-electrode and the shared electrode are spaced apart from each other at equal distances with respect to one point at which a first axis and a second axis intersect each other, wherein the first axis passes between the through-electrode and the shared electrode in a first direction parallel to the front surface or the back surface, and wherein the second axis passes through a center of the corresponding semiconductor chip in a second direction parallel to the front surface or the back surface.
11. 11 . The semiconductor package of claim 10 , wherein when the first and second semiconductor chips which are adjacent to each other are stacked such that the front surface of the first semiconductor chip and the back surface of the second semiconductor chip face each other, the through-electrode of the first semiconductor chip overlaps the through-electrode of the second semiconductor chip, adjacent thereto in the vertical direction, and the shared electrode of the first semiconductor chip overlaps the shared electrode of the first semiconductor chip, adjacent thereto in the vertical direction.
12. 12 . The semiconductor package of claim 11 , wherein the first and second semiconductor chips are stacked such that centers thereof overlap each other in the vertical direction.
13. 13 . The semiconductor package of claim 10 , wherein when the first and second semiconductor chips which are adjacent to each other are stacked such that the front surface of the first semiconductor chip and the front surface of the second semiconductor chip face each other, or such that the back surface of the first semiconductor chip and the back surface of the second semiconductor chip face each other, the through-electrode of the first semiconductor chip overlaps the shared electrode of the second semiconductor chip, adjacent thereto in the vertical direction, or the shared electrode of the first semiconductor chip overlaps the through-electrode of the second semiconductor chip, adjacent thereto in the vertical direction.
14. 14 . The semiconductor package of claim 13 , wherein the first and second semiconductor chips are stacked such that centers thereof are shifted from each other in the second direction.
15. 15 . The semiconductor package of claim 10 , wherein the one point is on a straight line connecting the through-electrode and the shared electrode to each other.
16. 16 . A semiconductor package comprising: a semiconductor chip including a semiconductor substrate, a circuit layer, a plurality of through-electrodes, and a plurality of shared electrodes, wherein the semiconductor substrate has a front surface and a back surface opposing each other, wherein the circuit layer includes a wiring structure disposed on the front surface, wherein the plurality of through-electrodes are electrically connected to the wiring structure and are arranged in a first direction parallel to the front surface or the back surface, wherein the plurality of shared electrodes are spaced apart from the plurality of through-electrodes in a second direction, intersecting the first direction, and are electrically connected to the plurality of through-electrodes, respectively, wherein on a plane, at least one pair of a through-electrode and a shared electrode, which are electrically connected to each other, among the plurality of through-electrodes and the plurality of shared electrodes are symmetrically arranged with respect to a point at which a first axis and a second axis intersect each other, wherein the first axis extends in the first direction between the plurality of through-electrodes and the plurality of shared electrodes, and wherein the second axis extends in the second direction and passes through a center of the semiconductor chip.
17. 17 . The semiconductor package of claim 16 , wherein each of the plurality of through-electrodes includes a front pad, a back pad, and a through via, wherein the front pad is disposed on the circuit layer, wherein the back pad is disposed on the back surface, and wherein the through via passes through the semiconductor substrate and electrically connects the front pad and the back pad to each other, and wherein each of the plurality of shared electrodes includes a front shared pad, a rear shared pad, and a shared via, wherein the front shared pad is disposed on the circuit layer, wherein the rear shared pad is disposed on the back surface, and wherein the shared via passes through the semiconductor substrate and electrically connects the front shared pad and the rear shared pad to each other.
18. 18 . The semiconductor package of claim 17 , wherein the through via and the shared via are connected to the front pad and the front shared pad through the wiring structure, respectively.
19. 19 . The semiconductor package of claim 16 , wherein the plurality of through-electrodes and the plurality of shared electrodes are electrically connected to each other through the wiring structure.
20. 20 . The semiconductor package of claim 16 , wherein the semiconductor chip further includes a rear wiring structure disposed on the back surface, and wherein the plurality of through-electrodes and the plurality of shared electrodes are electrically connected to each other through the rear wiring structure.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a Continuation of U.S. patent application Ser. No. 18/133,141, filed on Apr. 11, 2023, which claims priority from Korean Patent Application No. 10-2022-0088977 filed on Jul. 19, 2022, in the Korean Intellectual Property Office, the disclosure of which are incorporated herein by reference in their entireties herein. TECHNICAL FIELD The present inventive concept relates to a semiconductor package. DISCUSSION OF THE RELATED ART Generally, semiconductor devices included in electronic devices are relatively small in size and have relatively high performance and relatively high capacity. To implement such semiconductor devices, a semiconductor package for interconnecting semiconductor chips, which are stacked in a vertical direction, using a through-electrode (e.g., through silicon via) is under development. SUMMARY Example embodiments of the present inventive concept provide a semiconductor package in which semiconductor chips are stacked. According to an example embodiment of the present inventive concept, a semiconductor package includes: a first semiconductor chip including a plurality of first through-electrodes and a plurality of first shared electrodes, wherein the first through-electrodes are arranged in a first direction, wherein the plurality of first shared electrodes are spaced apart from the plurality of first through-electrodes in a second direction, intersecting the first direction, and are electrically connected to the plurality of first through-electrodes, respectively; and a second semiconductor chip including a plurality of second through-electrodes and a plurality of second shared electrodes, wherein the plurality of second through-electrodes are disposed on the first semiconductor chip and are arranged in the first direction, wherein the plurality of second shared electrodes are spaced apart from the plurality of second through-electrodes in the second direction and are electrically connected to the plurality of second through-electrodes, respectively, wherein a first through-electrode and a first shared electrode, which are electrically connected to each other, from among the plurality of first through-electrodes and the plurality of first shared electrodes are symmetrically arranged with respect to a first point at which a first axis, extending in the first direction and passing through a first center of the first semiconductor chip, and a second axis, extending in the second direction and passing through the first center of the first semiconductor chip, intersect, wherein a second through-electrode and a second shared electrode, which are electrically connected to each other, from among the plurality of second through-electrodes and the plurality of second shared electrodes are symmetrically arranged with respect to a second point at which a third axis, extending in the first direction and passing through a second center of the second semiconductor chip, and a fourth axis, extending in the second direction and passing through the second center of the second semiconductor chip, intersect, and wherein the first through-electrode and the first shared electrode are connected to at least one of the second through-electrode or the second shared electrode. According to an example embodiment of the present inventive concept, a semiconductor package includes: a plurality of semiconductor chips including a semiconductor substrate, a through-electrode, and a shared electrode, wherein the semiconductor substrate has a front surface and a back surface opposing each other, wherein the through-electrode penetrates through the semiconductor substrate, wherein the shared electrode penetrates through the semiconductor substrate and is electrically connected to the through-electrode, wherein the plurality of semiconductor chips are stacked in a direction substantially perpendicular to the front surface or the back surface, wherein the through-electrode and the shared electrode are spaced apart from each other at substantially equal distances with respect to one point at which a first axis, which passes between the through-electrode and the shared electrode, and a second axis, which passes through a center of a corresponding semiconductor chip among the plurality of semiconductor chips, intersect each other, and at least one of the through-electrode or the shared electrode of a first semiconductor chip of the plurality of semiconductor chips overlaps with at least one of the through-electrode or the shared electrode of a second semiconductor chip of the plurality of semiconductor chips adjacent in a vertical direction. According to an example embodiment of the present inventive concept, a semiconductor package includes: a semiconductor chip including a semiconductor substrate, a circuit layer, a plurality of through-electrodes, and a plurality of shared electrodes, wherein the semiconductor substrate has a front surface and a back surface opposing eac