US-20260130197-A1 - JUMPER GATE FOR ADVANCED INTEGRATED CIRCUIT STRUCTURES

Abstract

Jumper gates for advanced integrated circuit structures are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowire segments. A second vertical stack of horizontal nanowire segments is spaced apart from the first vertical stack of horizontal nanowire segments. A conductive structure is laterally between and in direct electrical contact with the first vertical stack of horizontal nanowire segments and with the second vertical stack of horizontal nanowire segments. A first source or drain structure is coupled to the first vertical stack of horizontal nanowire segments at a side opposite the conductive structure. A second source or drain structure is coupled to the second vertical stack of horizontal nanowire segments at a side opposite the conductive structure.

Inventors

• Sukru YEMENICIOUGLU
• Leonard P. GULER
• Gilbert Dewey
• Tahir Ghani

Assignees

• INTEL CORPORATION

Dates

Publication Date

20260507

Application Date

20260105

Claims (20)

1. 1 . An integrated circuit structure, comprising: a first vertical stack of horizontal nanowire segments; a second vertical stack of horizontal nanowire segments spaced apart from the first vertical stack of horizontal nanowire segments; a conductive structure laterally between the first vertical stack of horizontal nanowire segments and with the second vertical stack of horizontal nanowire segments; a first source or drain structure coupled to the first vertical stack of horizontal nanowire segments at a side opposite the conductive structure; and a second source or drain structure coupled to the second vertical stack of horizontal nanowire segments at a side opposite the conductive structure.
2. 2 . The integrated circuit structure of claim 1 , wherein the conductive structure is vertically over a sub-fin structure.
3. 3 . The integrated circuit structure of claim 1 , wherein the conductive structure has an uppermost surface above an uppermost surface of the first and second source or drain structures.
4. 4 . The integrated circuit structure of claim 1 , wherein the first and second source or drain structures have a semiconductor material composition different than a semiconductor material composition of the first and second vertical stacks of horizontal nanowire segments.
5. 5 . The integrated circuit structure of claim 4 , wherein the first and second source or drain structures comprise silicon and germanium, and the first and second vertical stacks of horizontal nanowire segments comprise silicon.
6. 6 . A method of fabricating an integrated circuit structure, the method comprising: forming vertical stack of horizontal nanowires; cutting the vertical stack of horizontal nanowires to form a first vertical stack of horizontal nanowire segments, and a second vertical stack of horizontal nanowire segments spaced apart from the first vertical stack of horizontal nanowire segments; forming a conductive structure laterally between the first vertical stack of horizontal nanowire segments and with the second vertical stack of horizontal nanowire segments; forming a first source or drain structure coupled to the first vertical stack of horizontal nanowire segments at a side opposite the conductive structure; and forming a second source or drain structure coupled to the second vertical stack of horizontal nanowire segments at a side opposite the conductive structure.
7. 7 . The method of claim 6 , wherein the conductive structure is vertically over a sub-fin structure.
8. 8 . The method of claim 6 , wherein the conductive structure has an uppermost surface above an uppermost surface of the first and second source or drain structures.
9. 9 . The method of claim 6 , wherein the first and second source or drain structures have a semiconductor material composition different than a semiconductor material composition of the first and second vertical stacks of horizontal nanowire segments.
10. 10 . The method of claim 9 , wherein the first and second source or drain structures comprise silicon and germanium, and the first and second vertical stacks of horizontal nanowire segments comprise silicon.
11. 11 . A computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure, the integrated circuit structure comprising: a first vertical stack of horizontal nanowire segments; a second vertical stack of horizontal nanowire segments spaced apart from the first vertical stack of horizontal nanowire segments; a conductive structure laterally between the first vertical stack of horizontal nanowire segments and with the second vertical stack of horizontal nanowire segments; a first source or drain structure coupled to the first vertical stack of horizontal nanowire segments at a side opposite the conductive structure; and a second source or drain structure coupled to the second vertical stack of horizontal nanowire segments at a side opposite the conductive structure.
12. 12 . The computing device of claim 11 , wherein the conductive structure is vertically over a sub-fin structure.
13. 13 . The computing device of claim 11 , wherein the conductive structure has an uppermost surface above an uppermost surface of the first and second source or drain structures.
14. 14 . The computing device of claim 11 , further comprising: a memory coupled to the board.
15. 15 . The computing device of claim 11 , further comprising: a communication chip coupled to the board.
16. 16 . The computing device of claim 11 , further comprising: a battery coupled to the board.
17. 17 . The computing device of claim 11 , further comprising: a camera coupled to the board.
18. 18 . The computing device of claim 11 , further comprising: a display coupled to the board.
19. 19 . The computing device of claim 11 , wherein the component is a packaged integrated circuit die.
20. 20 . The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 17/548,006, filed on Dec. 10, 2021, the entire contents of which is hereby incorporated by reference herein. TECHNICAL FIELD Embodiments of the disclosure are in the field of integrated circuit structures and processing and, in particular, jumper gates for advanced integrated circuit structures. BACKGROUND For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant. In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to scale down. In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and because they enable a less complicated tri-gate fabrication process. In another aspect, maintaining mobility improvement and short channel control as microelectronic device dimensions scale below the 10 nanometer (nm) node provides a challenge in device fabrication. Scaling multi-gate and nanowire transistors has not been without consequence, however. As the dimensions of these fundamental building blocks of microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on the lithographic processes used to pattern these building blocks have become overwhelming. In particular, there may be a trade-off between the smallest dimension of a feature patterned in a semiconductor stack (the critical dimension) and the spacing between such features. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A illustrates plan views representing a jumper gate for an SRAM device or a dummy device, and the foundation structure, in accordance with an embodiment of the present disclosure. FIG. 1B illustrates plan views representing various shorted dummy devices, in accordance with an embodiment of the present disclosure. FIG. 1C illustrates plan views representing various shorted SRAM devices, in accordance with an embodiment of the present disclosure. FIGS. 2A-2C illustrate cross-sectional views of various operations in a method of fabricating a gate-all-around integrated circuit structure with a jumper gate, in accordance with an embodiment of the present disclosure. FIG. 3 illustrates a cross-sectional view of a gate-all-around integrated circuit structure with a jumper gate, in accordance with an embodiment of the present disclosure. FIGS. 4A-4J illustrates cross-sectional views of various operations in a method of fabricating a gate-all-around integrated circuit structure, in accordance with an embodiment of the present disclosure. FIG. 5 illustrates a cross-sectional view of a non-planar integrated circuit structure as taken along a gate line, in accordance with an embodiment of the present disclosure. FIG. 6 illustrates cross-sectional views taken through nanowires and fins for a non-endcap architecture (left-hand side (a)) versus a self-aligned gate endcap (SAGE) architecture (right-hand side (b)), in accordance with an embodiment of the present disclosure. FIG. 7 illustrates cross-sectional views representing various operations in a method of fabricating a self-aligned gate endcap (SAGE) structure with gate-all-around devices, in accordance with an embodiment of the present disclosure. FIG. 8A illustrates a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure, in accordance with an embodiment of the present disclosure. FIG. 8B illustrates a cross-sectional source or drain view of the nanowire-based integrated circuit structure of FIG. 8A, as taken along the a-a′ axis, in accordance with an embodiment of the present disclosure. FIG. 8C illustrates a cross-sectional channel view of the nanowire-based integrated circuit structure of FIG. 8A, as taken along the b-b′ axis, in accordance with an embodiment of the present disclosure. FIG. 9 illustrates a computing device in accordance with one implementation of an embodiment of the disclosure. FIG. 10 illustrates an interposer that includes one or more embodiments of the disclosure. DESCRIPTION OF THE EMBODIMENTS Jumper gates for advanced integrated circuit structures are described. In the following description, numerous specific det