US-20260130198-A1 - SEMICONDUCTOR DEVICE AND METHOD FOR ANALYZING A FAILURE OF THE SAME

Abstract

A semiconductor device includes a substrate having a front surface and a rear surface. The device includes a first transistor disposed on the front surface of the substrate and including a first gate electrode and first source/drain patterns disposed adjacent to the first gate electrode. The device includes a front surface dummy stack structure disposed on the first transistor and electrically floated, the front surface dummy stack structure extending from a lower end to an upper end, the lower end being spaced apart from the first transistor. The front surface dummy stack structure includes alternately stacked front surface dummy vias front surface dummy wires that overlap the first gate electrode such that heat generated in the first transistor is transferred to the upper end of the front surface dummy stack structure through the plurality of front surface dummy vias and the plurality of front surface dummy wires.

Inventors

• Myungjin Chung
• Jinkyu Kim
• Eunguk CHUNG
• Keun Hwi Cho
• Suhaeng HEO

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20250624

Priority Date

20241101

Claims (20)

1. 1 . A semiconductor device comprising: a substrate including a front surface and a rear surface disposed opposed to the front surface along a vertical direction of the semiconductor device; a first transistor disposed on the front surface of the substrate and including a first gate electrode and first source/drain patterns disposed adjacent to the first gate electrode along a direction perpendicular to the vertical direction; and a front surface dummy stack structure disposed on the first transistor and electrically floated, the front surface dummy stack structure extending from a lower end to an upper end along the vertical direction, the lower end being spaced apart from the first transistor in the vertical direction, wherein the front surface dummy stack structure includes a plurality of front surface dummy vias and a plurality of front surface dummy wires, the plurality of front surface dummy vias and the plurality of front surface dummy wires being alternately stacked, and the plurality of front surface dummy vias and the plurality of front surface dummy wires of the front surface dummy stack structure overlap the first gate electrode in a vertical direction.
2. 2 . The semiconductor device of claim 1 , further comprising: a first wiring structure connected to one of the first source/drain patterns and the first gate electrode; and an upper insulating layer covering the first wiring structure and the front surface dummy stack structure, wherein the first wiring structure includes a plurality of front surface vias and a plurality of front surface wires, and an upper end of the first wiring structure is disposed at a same level along the vertical direction as the upper end of the front surface dummy stack structure.
3. 3 . The semiconductor device of claim 2 , wherein an uppermost front surface wire of the plurality of front surface wires does not overlap the plurality of front surface dummy vias and the plurality of front surface dummy wires in the vertical direction.
4. 4 . The semiconductor device of claim 2 , further comprising a support substrate on the upper insulating layer.
5. 5 . The semiconductor device of claim 1 , wherein the first transistor is included in a first flip-flop circuit.
6. 6 . The semiconductor device of claim 5 , wherein the first gate electrode of the first transistor is configured to receive a test signal input.
7. 7 . The semiconductor device of claim 1 , further comprising: a power wire disposed on the rear surface of the substrate, wherein the power wire is connected to one of the first source/drain patterns of the first transistor.
8. 8 . The semiconductor device of claim 1 , further comprising: a second transistor that is disposed on the front surface of the substrate and includes a second gate electrode and second source/drain patterns adjacent to the second gate electrode; a first power wire disposed on the rear surface of the substrate and connected to one of the second source/drain patterns; and a rear surface dummy stack structure disposed on the rear surface of the substrate and electrically floated, the rear surface dummy stack structure extending from a lower end to an upper end along the vertical direction, the upper end being spaced apart from the second transistor in the vertical direction, wherein the rear surface dummy stack structure includes a plurality of rear surface dummy vias and a plurality of rear surface dummy wires, the plurality of rear surface dummy vias and the plurality of rear surface dummy wires being alternately stacked, and the plurality of rear surface dummy vias and the plurality of rear surface dummy wires of the rear surface dummy stack structure overlap the second gate electrode in the vertical direction.
9. 9 . The semiconductor device of claim 8 , further comprising: a second wiring structure that is disposed on the rear surface of the substrate and connected to the first power wire, wherein the second wiring structure includes a plurality of rear surface vias and a plurality of rear surface wires, the plurality of rear surface vias and the plurality of rear surface wires being alternately stacked, and a lower end of the second wiring structure is disposed at a same level along the vertical direction as the lower end of the rear surface dummy stack structure.
10. 10 . The semiconductor device of claim 9 , further comprising: a rear surface insulating layer that is disposed on the rear surface of the substrate and covering the lower end of the second wiring structure and the lower end of the rear surface dummy stack structure; and an external connection terminal penetrating the rear surface insulating layer to be connected to the lower end of the second wiring structure.
11. 11 . The semiconductor device of claim 8 , wherein the second transistor is included in a second flip-flop circuit.
12. 12 . The semiconductor device of claim 11 , wherein the second gate electrode of the second transistor is configured to receive a test signal input.
13. 13 . The semiconductor device of claim 1 , wherein an uppermost front surface dummy wire of the plurality of front surface dummy wires has a width greater than a width of a lowermost front surface dummy wire of the plurality of front surface dummy wires.
14. 14 . A semiconductor device comprising: a substrate including a front surface and a rear surface opposed to the front surface along a vertical direction of the semiconductor device; a first transistor that is disposed on the front surface of the substrate and includes a first gate electrode and first source/drain patterns adjacent to the first gate electrode; a first power wire that is disposed on the rear surface of the substrate and connected to one of the first source/drain patterns; and a rear surface dummy stack structure disposed on the rear surface of the substrate and electrically floated, the rear surface dummy stack structure extending from a lower end to an upper end along the vertical direction, the upper end being spaced apart from the first transistor in the vertical direction, wherein the rear surface dummy stack structure includes a plurality of rear surface dummy vias and a plurality of rear surface dummy wires, the plurality of rear surface dummy vias and the plurality of rear surface dummy wires being alternately stacked, and the plurality of rear surface dummy vias and the plurality of rear surface dummy wires of the rear surface dummy stack structure overlap the first gate electrode in the vertical direction.
15. 15 . The semiconductor device of claim 14 , wherein the first transistor is included in a first flip-flop circuit.
16. 16 . The semiconductor device of claim 15 , wherein the first gate electrode of the first transistor is configured to receive a test signal input.
17. 17 . The semiconductor device of claim 14 , further comprising a first wiring structure that is disposed on the rear surface of the substrate and connected to the first power wire, wherein the first wiring structure includes a plurality of rear surface vias and a plurality of rear surface wires, the plurality of rear surface vias and the plurality of rear surface wires being alternately stacked, and a lower end of the first wiring structure is disposed at a same level along the vertical direction as the lower end of the rear surface dummy stack structure.
18. 18 . The semiconductor device of claim 17 , further comprising: a rear surface insulating layer that is disposed on the rear surface of the substrate and covers the lower end of the first wiring structure and the lower end of the rear surface dummy stack structure; and an external connection terminal penetrating the rear surface insulating layer to be connected to the lower end of the first wiring structure.
19. 19 . A semiconductor device comprising: a substrate including a front surface and a rear surface opposed to the front surface along a vertical direction of the semiconductor device; a first flip-flop circuit and a second flip-flop circuit disposed on the front surface of the substrate, wherein the first flip-flop circuit comprises a first transistor that is disposed on the front surface of the substrate and includes a first gate electrode and first source/drain patterns adjacent to the first gate electrode, and wherein the second flip-flop circuit comprises a second transistor that is disposed on the front surface of the substrate and includes a second gate electrode and second source/drain patterns adjacent to the second gate electrode; a front surface dummy stack structure disposed on the first transistor and electrically floated, the front surface dummy stack structure extending from a lower end to an upper end along the vertical direction, the lower end being spaced apart from the first transistor in the vertical direction; a first wiring structure disposed on the front surface of the substrate and connected to one of the first source/drain patterns and the first gate electrode; a first power wire disposed on the rear surface of the substrate and connected to one of the second source/drain patterns; a rear surface dummy stack structure disposed on the rear surface of the substrate and electrically floated; and a second wiring structure disposed on the rear surface of the substrate and connected to the first power wire, wherein the front surface dummy stack structure includes a plurality of front surface dummy vias and a plurality of front surface dummy wires, the plurality of front surface dummy vias and the plurality of front surface dummy wires being alternately stacked, the plurality of front surface dummy vias and the plurality of front surface dummy wires of the front surface dummy stack structure overlap the first gate electrode in the vertical direction, the rear surface dummy stack structure includes a plurality of rear surface dummy vias and a plurality of rear surface dummy wires, the plurality of rear surface dummy vias and the plurality of rear surface dummy wires being alternately stacked, and the plurality of rear surface dummy vias and the plurality of rear surface dummy wires of the rear surface dummy stack structure overlap the second gate electrode in the vertical direction.
20. 20 . The semiconductor device of claim 19 , wherein the first wiring structure comprises a plurality of front surface vias and a plurality of front surface wires, the plurality of front surface vias and the plurality of front surface wires being alternately stacked, an upper end of the first wiring structure is disposed at a same first level along the vertical direction as the upper end of the front surface dummy stack structure, an uppermost front surface wire of the plurality of front surface wires does not overlap the plurality of front surface dummy wires in a vertical direction, the second wiring structure comprises a plurality of rear surface vias and a plurality of rear surface wires, the plurality of rear surface vias and the plurality of rear surface wires being alternately stacked, a lower end of the second wiring structure is disposed at a same second level along the vertical direction as a lower end of the rear surface dummy stack structure, and a lowermost rear surface wire of the plurality of rear surface wires does not overlap the plurality of rear surface dummy wires in a vertical direction.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 of Korean Patent Application No. 10-2024-0153290, filed on Nov. 1, 2024, the entire contents of which are hereby incorporated by reference. FIELD The present disclosure relates to a semiconductor device and a method for analyzing a failure of the same. BACKGROUND A semiconductor device may include an integrated circuit composed of metal-oxide-semiconductor field effect transistors (MOSFETs). As a size and a design rule of the semiconductor device gradually decrease, scaling down of the MOSFETs is being accelerated. When the sizes of the MOSFETs decrease, a defect or failure of the semiconductor device may occur. Failure analysis is widely used in the semiconductor industry, and the defects of the semiconductor devices such as integrated circuits may be detected. However, as designs of the semiconductor devices become more complicated, defect detection accuracy is being deteriorated. SUMMARY The present disclosure provides a semiconductor device in which a failure thereof can be easily analyzed. The present disclosure also provides a method for analyzing a failure of a semiconductor device with improved consistency. An embodiment consistent with the present disclosure provides a semiconductor device including a substrate including a front surface and a rear surface opposed to each other, a first transistor disposed on the front surface of the substrate, and including a first gate electrode and first source/drain patterns adjacent to both sides thereof, and a front surface dummy stack structure located on the first transistor, and electrically floated, wherein the front surface dummy stack structure includes front surface dummy vias and front surface dummy wires alternately stacked, and the front surface dummy vias and the front surface dummy wires that constitute the front surface dummy stack structure vertically overlap the first gate electrode. In an embodiment consistent with the present disclosure, a semiconductor device includes a substrate including a front surface and a rear surface opposed to each other, a first transistor disposed on the front surface of the substrate, and including a first gate electrode and first source/drain patterns adjacent to both sides thereof, a first power wire disposed on the rear surface of the substrate, and connected to one of the first source/drain patterns, and a rear surface dummy stack structure disposed on the rear surface of the substrate, and electrically floated, wherein the rear surface dummy stack structure includes rear surface dummy vias and rear surface dummy wires alternately stacked, and the rear surface dummy vias and the rear surface dummy wires that constitute the rear surface dummy stack structure vertically overlap the first gate electrode. In an embodiment consistent with the present disclosure, a semiconductor device includes a substrate including a front surface and a rear surface opposed to each other, a first flip-flop circuit and a second flip-flop circuit disposed on the front surface of the substrate, a first transistor disposed on the front surface of the substrate, including a first gate electrode and first source/drain patterns adjacent to both sides thereof, and included in the first flip-flop circuit, a second transistor disposed on the front surface of the substrate, including a second gate electrode and second source/drain patterns adjacent to both sides thereof, and included in the second flip-flop circuit, a front surface dummy stack structure located on the first transistor, and electrically floated, a first wiring structure disposed on the front surface of the substrate, and connected to one of the first source/drain patterns and the first gate electrode, a first power wire disposed on the rear surface of the substrate, and connected to one of the second source/drain patterns, a rear surface dummy stack structure disposed on the rear surface of the substrate, and electrically floated, and a second wiring structure disposed on the rear surface of the substrate, and connected to the first power wire, wherein the front surface dummy stack structure includes front surface dummy vias and front surface dummy wires alternately stacked, the front surface dummy vias and the front surface dummy wires that constitute the front surface dummy stack structure vertically overlap the first gate electrode, the rear surface dummy stack structure includes rear surface dummy vias and rear surface dummy wires alternately stacked, and the rear surface dummy vias and the rear surface dummy wires that constitute the rear surface dummy stack structure vertically overlap the second gate electrode. In an embodiment consistent with the present disclosure, a method for analyzing a failure of a semiconductor device includes manufacturing a semiconductor device including a front surface dummy stack structure disposed on a substrate and a rea