US-20260130199-A1 - SEMICONDUCTOR DEVICE INCLUDING THROUGH VIA

US20260130199A1US 20260130199 A1US20260130199 A1US 20260130199A1US-20260130199-A1

Abstract

A semiconductor device according to example embodiments of the present disclosure may include: a first structure; and a second structure having a peripheral circuit region, and the first structure may include: memory cells; and a cell routing interconnection line electrically connected to the memory cells, and the second structure may include: a semiconductor body; a rear insulating layer disposed on a lower surface of the semiconductor body; a first peripheral transistor; a first through-insulating pattern penetrating through the semiconductor body; and a through-via penetrating through the first through-insulating pattern and electrically connected to the cell routing interconnection line, and the first through-insulating pattern may include a first insulating pattern including a first portion adjacent to the rear insulating layer and a second portion disposed on the first portion, and a second insulating pattern disposed between a side surface of the second portion and the semiconductor body.

Inventors

Jungryul LEE
Donghoon KWON

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20250912
Priority Date: 20241105

Claims (20)

1 . A semiconductor device, comprising: a first structure having a memory region; and a second structure vertically overlapping the first structure and having a peripheral circuit region, wherein the first structure includes: a plurality of memory cells disposed within the memory region, each memory cell of the plurality of memory cells including a vertical channel transistor and an information storage structure; and a cell routing interconnection line electrically connected to the plurality of memory cells, and wherein the second structure includes: a semiconductor body; a rear insulating layer below the semiconductor body; a device isolating pattern defining a peripheral active region of the semiconductor body and having a lower surface at a higher vertical level than a vertical level of a lower surface of the semiconductor body; a first through-insulating pattern penetrating through the semiconductor body, the first through-insulating pattern including a first insulating pattern including a first portion and a second portion over the first portion; and a second insulating pattern between the second portion of the first insulating pattern and the semiconductor body, over the first portion of the first insulating pattern; a second through-insulating pattern penetrating through the device isolating pattern and the semiconductor body below the device isolating pattern; a peripheral transistor including a first peripheral source/drain and a second peripheral source/drain disposed within the peripheral active region, a peripheral channel region between the first peripheral source/drain and the second peripheral source/drain, and a peripheral gate disposed on the peripheral channel region; and a through-via penetrating through the first through-insulating pattern and electrically connected to the cell routing interconnection line.
2 . The semiconductor device of claim 1 , wherein a lower surface of the semiconductor body, a lower surface of the first through-insulating pattern, and a lower surface of the second through-insulating pattern are coplanar with each other.
3 . The semiconductor device of claim 1 , wherein an upper surface of the first through-insulating pattern, an upper surface of the second through-insulating pattern, and an upper surface of the semiconductor body are coplanar with each other.
4 . The semiconductor device of claim 1 , wherein the first portion is adjacent to the rear insulating layer and the second portion extends upward from the first portion; and such that the first portion of the first insulating pattern separates the second insulating pattern from the rear insulating layer.
5 . The semiconductor device of claim 4 , wherein the first insulating pattern includes a first insulating material, and the second insulating pattern includes a second insulating material different from the first insulating material.
6 . The semiconductor device of claim 4 , wherein an upper surface of the first portion of the first insulating pattern includes a first region from which the second portion of the first insulating pattern extends and a second region excluding the first region, and the second region of the upper surface of the first portion is in contact with the semiconductor body.
7 . The semiconductor device of claim 1 , wherein a lower surface of the first through-insulating pattern has a first width in a first direction, and a lower surface of the second through-insulating pattern has a second width that is smaller than the first width in the first direction.
8 . The semiconductor device of claim 1 , wherein the second through-insulating pattern includes: a third insulating pattern including a third portion adjacent to the rear insulating layer and a fourth portion over and extending from the third portion; and a fourth insulating pattern between the fourth portion of the third insulating pattern and the semiconductor body, over the third portion of the third insulating pattern.
9 . The semiconductor device of claim 8 , wherein an upper surface of the third portion of the third insulating pattern includes a third region from which the fourth portion of the third insulating pattern extends, and a fourth region excluding the third region, and the fourth region of the upper surface of the third portion is in contact with the semiconductor body.
10 . The semiconductor device of claim 8 , wherein a lower surface of the fourth insulating pattern of the second through-insulating pattern is at a lower vertical level than a lower surface of the device isolating pattern.
11 . The semiconductor device of claim 1 , wherein the device isolating pattern includes a first device isolating insulating film, a second device isolating insulating film in contact with a side surface and a lower surface of the first device isolating insulating film, and a third device isolating insulating film in contact with a side surface and a lower surface of the second device isolating insulating film, the first device isolating insulating film and the third device isolating insulating film include a third insulating material, and the second device isolating insulating film includes a fourth insulating material different from the third insulating material.
12 . The semiconductor device of claim 11 , wherein the first through-insulating pattern includes a first through-insulating film, a second through-insulating film in contact with a side surface and a lower surface of the first through-insulating film, and a third through-insulating film in contact with a side surface and a lower surface of the second through-insulating film, the first through-insulating film and the third through-insulating film include the third insulating material, and the second through-insulating film includes the fourth insulating material.
13 . A semiconductor device, comprising: a first structure having a memory region; and a second structure vertically overlapping the first structure and having a peripheral circuit region, wherein the first structure includes: a plurality of memory cells disposed within the memory region; and a cell routing interconnection line electrically connected to the plurality of memory cells, and wherein the second structure includes: a semiconductor body; a rear insulating layer disposed on a lower surface of the semiconductor body; a first peripheral transistor including a first peripheral source/drain and a second peripheral source/drain disposed within a first peripheral active region of the semiconductor body, a first peripheral channel region between the first peripheral source/drain and the second peripheral source/drain, and a first peripheral gate disposed on the first peripheral channel region; a first through-insulating pattern penetrating through the semiconductor body; a device isolating pattern having a lower surface at a vertical level higher than a lower surface of the semiconductor body within the semiconductor body and spaced apart from the first through-insulating pattern in a horizontal direction; and a through-via penetrating through the first through-insulating pattern and the rear insulating layer and electrically connected to the cell routing interconnection line, wherein the first through-insulating pattern includes a first insulating pattern including a first portion adjacent to the rear insulating layer and a second portion disposed on the first portion, and a second insulating pattern disposed between a side surface of the second portion of the first insulating pattern and the semiconductor body.
14 . The semiconductor device of claim 13 , wherein a side surface of the first portion of the first insulating pattern is in contact with the semiconductor body.
15 . The semiconductor device of claim 13 , wherein the first insulating pattern includes silicon oxide, and the second insulating pattern includes silicon nitride.
16 . The semiconductor device of claim 13 , wherein the device isolating pattern includes a first device isolating insulating film, a second device isolating insulating film in contact with a side surface and a lower surface of the first device isolating insulating film, and a third device isolating insulating film in contact with a side surface and a lower surface of the second device isolating insulating film, the first insulating pattern of the first through-insulating pattern, the first device isolating insulating film, and the third device isolating insulating film include a first insulating material, and the second insulating pattern of the first through-insulating pattern and the second device isolating insulating film include a second insulating material different from the first insulating material.
17 . The semiconductor device of claim 13 , wherein the second structure further includes: a second peripheral transistor including a third peripheral source/drain and a fourth peripheral source/drain disposed within of a second peripheral active region of the semiconductor body, a second peripheral channel region between the third peripheral source/drain and the fourth peripheral source/drain, and a second peripheral gate disposed on the second peripheral channel region of the second peripheral active region, and the device isolating pattern is disposed between the first peripheral transistor and the second peripheral transistor.
18 . The semiconductor device of claim 13 , wherein the second structure further includes a second through-insulating pattern penetrating through the device isolating pattern and penetrating through the semiconductor body below the device isolating pattern, and the second through-insulating pattern includes: a third insulating pattern including a third portion over and adjacent to the rear insulating layer and a fourth portion extending from the third portion; and a fourth insulating pattern between the fourth portion of the third insulating pattern and the semiconductor body, over the third portion of the third insulating pattern.
19 . A semiconductor device, comprising: a first structure having a plurality of memory cells disposed in a memory region and a cell routing interconnection line electrically connected to the plurality of memory cells; and a second structure vertically overlapping the first structure and having a peripheral circuit region, wherein the second structure includes: a semiconductor body; a device isolating pattern defining a peripheral active region of the semiconductor body; a first through-insulating pattern penetrating through the semiconductor body; a peripheral transistor including a first peripheral source/drain and a second peripheral source/drain disposed within the peripheral active region, a peripheral channel region between the first peripheral source/drain and the second peripheral source/drain, and a peripheral gate disposed on the peripheral channel region; and a through-via penetrating through the first through-insulating pattern and electrically connected to the cell routing interconnection line, and the first through-insulating pattern includes a first insulating pattern having a first portion having a lower surface coplanar with a lower surface of the semiconductor body and a second portion disposed on the first portion, and a second insulating pattern on a side surface of the second portion of the first insulating pattern.
20 . The semiconductor device of claim 19 , wherein a first height of the first portion of the first insulating pattern in a vertical direction is smaller than a second height of the second portion of the first insulating pattern in the vertical direction.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This U.S. non-provisional application claims benefit of priority to Korean Patent Application No. 10-2024-0154860 filed on Nov. 5, 2024 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND The present disclosure relates to a semiconductor device including a through-via. Research is being conducted so as to reduce the size of elements included in semiconductor devices and improve performance thereof. For example, in DRAM, research is being conducted so as to reliably and stably form reduced-size elements, but with a decrease in the size of the elements, the performance of semiconductor devices has been deteriorated. SUMMARY An aspect of the present disclosure is to provide a device having improved reliability. However, the object of the present invention is not limited to the above-described objects, and may be variously extended without departing from the spirit and domain of the present disclosure. A semiconductor device according to example embodiments of the present disclosure may include a first structure having a memory region; and a second structure vertically overlapping the first structure and having a peripheral circuit region, and the first structure may include: a plurality of memory cells disposed within the memory region, each memory cell of the plurality of memory cells including a vertical channel transistor and an information storage structure; and a cell routing interconnection line electrically connected to the plurality of memory cells, and the second structure may include: a semiconductor body; a rear insulating layer below the semiconductor body; a device isolating pattern defining a peripheral active region of the semiconductor body and having a lower surface at a higher vertical level than a vertical level of a lower surface of the semiconductor body, the device isolating patterns comprising a first device isolating pattern; a first through-insulating pattern penetrating through the semiconductor body, the first through-insulating pattern including a first insulating pattern including a first portion and a second portion over the first portion, and a second insulating pattern between the second portion of the first insulating pattern and the semiconductor body, over the first portion of the first insulating pattern; a second through-insulating pattern penetrating through the first device isolating pattern and the semiconductor body below the first device isolating pattern; a peripheral transistor including a first peripheral source/drain and a second peripheral source/drain disposed within the peripheral active region, a peripheral channel region between the first peripheral source/drain and the second peripheral source/drain, and a peripheral gate disposed on the peripheral channel region; and a through-via penetrating through the first through-insulating pattern and electrically connected to the cell routing interconnection line. A semiconductor device according to example embodiments of the present disclosure may include: a first structure having a memory region; and a second structure vertically overlapping the first structure and having a peripheral circuit region, and the first structure may include: a plurality of memory cells disposed within the memory region; and a cell routing interconnection line electrically connected to the plurality of memory cells, and the second structure may include: a semiconductor body; a rear insulating layer disposed on a lower surface of the semiconductor body; a first peripheral transistor including a first peripheral source/drain and a second peripheral source/drain disposed within a first peripheral active region of the semiconductor body, a first peripheral channel region between the first peripheral source/drain and the second peripheral source/drain, and a first peripheral gate disposed on the first peripheral channel region; a first through-insulating pattern penetrating through the semiconductor body; a device isolating pattern having a lower surface disposed at a vertical level higher than a lower surface of the semiconductor body within the semiconductor body and spaced apart from the first through-insulating pattern in a horizontal direction; and a through-via penetrating through the first through-insulating pattern and the rear insulating layer and electrically connected to the cell routing interconnection line, and the first through-insulating pattern may include a first insulating pattern including a first portion adjacent to the rear insulating layer and a second portion disposed on the first portion, and a second insulating pattern disposed between a side surface of the second portion of the first insulating pattern and the semiconductor body. A semiconductor device according to example embodiments may include: a first structure having a plurality of memory cells disposed in a memory region and a cell routing in