US-20260130200-A1 - Methods of Forming Interconnect Structures in Semiconductor Fabrication

US20260130200A1US 20260130200 A1US20260130200 A1US 20260130200A1US-20260130200-A1

Abstract

A semiconductor structure includes a first dielectric layer, a first via and a second via disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer, the first via, and the second via, a first conductive line disposed on the first via and in a bottom portion of the second dielectric layer, a second conductive line disposed on the second via and in the bottom portion of the second dielectric layer, a first barrier layer extending along sidewalls and a top surface of the first conductive line, and a second barrier layer extending along sidewalls and a top surface of the second conductive line. The bottom portion of the second dielectric layer includes an air gap between the first conductive line and the second conductive line.

Inventors

Ming-Han Lee
Shau-Lin Shue

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20251229

Claims (20)

1 . A semiconductor structure, comprising: a first dielectric layer; a first via and a second via disposed in the first dielectric layer; a second dielectric layer disposed over the first dielectric layer, the first via, and the second via; a first conductive line disposed on the first via and in a bottom portion of the second dielectric layer; a second conductive line disposed on the second via and in the bottom portion of the second dielectric layer; a first barrier layer extending along sidewalls and a top surface of the first conductive line; and a second barrier layer extending along sidewalls and a top surface of the second conductive line, wherein the bottom portion of the second dielectric layer comprises an air gap between the first conductive line and the second conductive line.
2 . The semiconductor structure of claim 1 , further comprising: a third dielectric layer below the first dielectric layer, the first via, and the second via; and a first conductive feature and a second conductive feature in the third dielectric layer, wherein the first conductive feature is below and connected to the first via, wherein the second conductive feature is below and connected to the second via.
3 . The semiconductor structure of claim 1 , wherein the first via comprises a bulk layer in contact with the first dielectric layer.
4 . The semiconductor structure of claim 1 , wherein the air gap is laterally between the first conductive line and the second conductive line.
5 . The semiconductor structure of claim 1 , further comprising: a third via disposed on the first conductive line and in a top portion of the second dielectric layer; and a fourth via disposed on the second conductive line and in a top portion of the second dielectric layer.
6 . The semiconductor structure of claim 1 , wherein the first via comprises a third barrier layer and a bulk layer over the third barrier layer, wherein the third barrier layer is on sidewalls of the bulk layer.
7 . The semiconductor structure of claim 6 , wherein a bottom surface of the bulk layer directly contacts a conductive feature below the first via.
8 . The semiconductor structure of claim 6 , wherein a portion of the third barrier layer is on a top surface of the first dielectric layer.
9 . A semiconductor structure, comprising: a first dielectric layer; a first conductive feature in the first dielectric layer; a second dielectric layer over the first dielectric layer and the first conductive feature; a second conductive feature in a bottom portion of the second dielectric layer and contacting the first conductive feature; and a third conductive feature in a top portion of the second dielectric layer and contacting the second conductive feature, wherein the bottom portion and the top portion of the second dielectric layer are portions of a continuous layer, and wherein the second conductive feature comprises a bulk layer and a barrier layer extending along a top surface and sidewalls of the bulk layer.
10 . The semiconductor structure of claim 9 , wherein the bulk layer is a first bulk layer and the barrier layer is a first barrier layer, wherein the first conductive feature comprises a second barrier layer and a second bulk layer on sidewalls the second barrier layer.
11 . The semiconductor structure of claim 10 , wherein the second bulk layer is on a top surface of the second barrier layer.
12 . The semiconductor structure of claim 10 , wherein the second barrier layer is free of contact with the first barrier layer.
13 . The semiconductor structure of claim 10 , wherein the second barrier layer comprises a portion extending on a top surface of the first dielectric layer, wherein the portion of the second barrier layer contacts the first barrier layer.
14 . The semiconductor structure of claim 9 , wherein the bulk layer is a first bulk layer and the barrier layer is a first barrier layer, wherein the third conductive feature comprises a second barrier layer and a second bulk layer over the second barrier layer, wherein the second barrier layer is disposed on sidewalls of the second dielectric layer and on a top surface of the first barrier layer.
15 . The semiconductor structure of claim 9 , further comprising a dielectric material embedded in the bottom portion of the second dielectric layer and adjacent to the second conductive feature, wherein the dielectric material has a composition different from a composition of the second dielectric layer.
16 . A method, comprising: providing a first dielectric layer; forming a first conductive feature in the first dielectric layer; forming a second conductive feature on the first conductive feature and the first dielectric layer, wherein the second conductive feature comprises a bulk layer on the first conductive feature and a barrier layer over a top surface and sidewalls of the bulk layer; thereafter, depositing a second dielectric layer over the first dielectric layer and the barrier layer of the second conductive feature; patterning the second dielectric layer to form an opening exposing the barrier layer; and forming a third conductive feature in the opening.
17 . The method of claim 16 , wherein the second dielectric layer is deposited on sidewalls of the barrier layer.
18 . The method of claim 16 , wherein forming the second conductive feature comprises: depositing a conductive layer over the first conductive feature and the first dielectric layer; forming a patterned mask directly above the first conductive feature; and patterning the conductive layer, thereby forming the second conductive feature.
19 . The method of claim 16 , wherein the bulk layer is a first bulk layer, the barrier layer is a first barrier layer, and the opening is a first opening; and wherein forming the first conductive feature comprises: patterning the first dielectric layer to form a second opening, depositing a second barrier layer in the second opening, and depositing a second bulk layer over the second barrier layer, thereby forming the first conductive feature.
20 . The method of claim 19 , wherein depositing the second barrier layer comprises selectively depositing the second barrier layer on sidewalls of the second opening and on a top surface of the first dielectric layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 18/641,745 filed Apr. 22, 2024, which is a continuation of U.S. patent application Ser. No. 17/402,942 filed Aug. 16, 2021, now issued U.S. Pat. No. 11,967,552, which is a divisional of U.S. patent application Ser. No. 16/534,411 filed Aug. 7, 2019, now issued U.S. Pat. No. 11,094,626, which claims priority to U.S. Provisional Patent Application Ser. No. 62/735,520 filed on Sep. 24, 2018, each of which is herein incorporated by reference in its entirety. BACKGROUND The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that may be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, copper-based interconnect structures typically implemented in multilayer interconnect (MLI) features have presented performance, yield, and cost challenges as MLI features become more compact with ever-shrinking IC feature size. For example, interconnect structures thus formed have been observed to exhibit higher aspect ratios, resistivity, and line-to-line capacitance; cause damages in surrounding ILD layer(s); and develop voids, collapse, and/or bend during patterning and deposition processes. Accordingly, although existing interconnect structures have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a fragmentary diagrammatic view of an integrated circuit device, in portion or entirety, according to various aspects of the present disclosure. FIG. 2A is an enlarged fragmentary diagrammatic view of the integrated circuit device of FIG. 1 when implementing an interconnect structure, in portion or entirety, according to various aspects of the present disclosure. FIG. 2B is an enlarged fragmentary diagrammatic view of the integrated circuit device of FIG. 1 when implementing another interconnect structure, in portion or entirety, according to various aspects of the present disclosure. FIG. 2C is an enlarged fragmentary diagrammatic view of the integrated circuit device of FIG. 1 when implementing yet another interconnect structure, in portion or entirety, according to various aspects of the present disclosure. FIG. 3A is a flow chart of a method for fabricating an interconnect structure, such as the interconnect structures depicted in FIG. 1 and/or FIGS. 2A-2C, according to various aspects of the present disclosure. FIG. 3B is a flow chart of a method for fabricating a via of an interconnect structure, such as the interconnect structures depicted in FIG. 1 and/or FIGS. 2A-2C, according to various aspects of the present disclosure. FIG. 3C is a flow chart of a method for fabricating a conductive line of an interconnect structure, such as the interconnect structures depicted in FIG. 1 and/or FIGS. 2A-2C, according to various aspects of the present disclosure. FIGS. 4, 5, 6, 7, 8, 9, 10, 11, 12, 13A, 13B, 14, 15, and 16 are fragmentary diagrammatic views of an interconnect structure, in portion or entirety, at various fabrication stages (such as those associated with the method of FIGS. 3A, 3B, and/or 3C) according to various aspects of the present disclosure. DETAILED DESCRIPTION The present disclosure relates generally to integrated circuit devices, and more particularly, to interconnect structures for integrated circuit devices. The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct co