US-20260130201-A1 - SEMICONDUCTOR DEVICE INCLUDING RECESSED INTERCONNECT STRUCTURE

Abstract

A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.

Inventors

• Guo-Huei Wu
• Hui-Zhong ZHUANG
• Chih-Liang Chen
• Cheng-Chi Chuang
• Shang-Wen Chang
• Yi-Hsun CHIU

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260507

Application Date

20260105

Claims (20)

1. 1 . A semiconductor device, comprising: a first gate structure extending along a first lateral direction; a second gate structure extending along the first lateral direction and spaced from the first gate structure along a second lateral direction perpendicular to the first lateral direction; a contact structure including a first portion with a first height and a second portion with a second height, the second height being higher than the first height; and a first interconnect structure extending along the second lateral direction; wherein the contact structure is configured to electrically connect the first gate structure to the first interconnect structure by contacting the first gate structure through its first portion and contacting the first interconnect structure through its second portion.
2. 2 . The semiconductor device of claim 1 , further comprising: a source/drain structure disposed on one of two sides of the first gate structure along the second lateral direction; wherein the source/drain structure is substantially aligned with the second portion of the contact structure along a vertical direction.
3. 3 . The semiconductor device of claim 2 , wherein the source/drain structure is electrically isolated from the second portion of the contact structure.
4. 4 . The semiconductor device of claim 2 , wherein the source/drain structure is interposed between the first gate structure and the second gate structure along the second lateral direction.
5. 5 . The semiconductor device of claim 1 , further comprising: a third gate structure extending along the first lateral direction, and disposed opposite the first gate structure from the second gate structure along the second lateral direction.
6. 6 . The semiconductor device of claim 5 , wherein the third gate structure is electrically coupled to a second interconnect structure extending along the second lateral direction.
7. 7 . The semiconductor device of claim 6 , wherein the second interconnect structure and the first interconnect structure are disposed in the same interconnect layer.
8. 8 . The semiconductor device of claim 5 , wherein the first gate structure and the third gate structure are spaced apart from each other by a distance along the second lateral direction, and wherein a width by which at least the first interconnect structure and the second interconnect structure is extended along the second lateral direction is equal to or greater than 1.5 times the distance.
9. 9 . The semiconductor device of claim 1 , wherein the first gate structure and the second gate structure are adjacent two of a number of gate structures that constitute a standard cell, the number being equal to or less than 5.
10. 10 . The semiconductor device of claim 9 , wherein the first interconnect structure is included in one of a number of signal tracks disposed in an interconnect layer, the number being equal to or less than 3.
11. 11 . A semiconductor device, comprising: a first gate structure extending along a first lateral direction; a second gate structure extending along the first lateral direction and spaced from the first gate structure along a second lateral direction perpendicular to the first lateral direction; a source/drain structure interposed between the first gate structure and the second gate structure along the second lateral direction; a contact structure including a first portion and a second portion; and a first interconnect structure extending along the second lateral direction; wherein the contact structure is configured to electrically connect the first gate structure to the first interconnect structure, and wherein the first portion of the contact structure is vertically disposed over the first gate structure and the second portion of the contact structure is vertically disposed over the source/drain structure.
12. 12 . The semiconductor device of claim 11 , wherein the first portion of the contact structure has a first height and the second portion of the contact structure has a second height, and wherein the second height is higher than the first height.
13. 13 . The semiconductor device of claim 11 , wherein the first gate structure is connected only to the first portion of the contact structure, and the first interconnect structure is connected only to the second portion of the contact structure.
14. 14 . The semiconductor device of claim 11 , wherein the first gate structure and the second gate structure are adjacent two of a number of gate structures that constitute a standard cell, the number being equal to or less than 5.
15. 15 . The semiconductor device of claim 14 , wherein the first interconnect structure is included in one of a number of signal tracks disposed in an interconnect layer, the number being equal to or less than 3.
16. 16 . The semiconductor device of claim 11 , further comprising: a third gate structure extending along the first lateral direction, and disposed opposite the first gate structure from the second gate structure along the second lateral direction.
17. 17 . The semiconductor device of claim 16 , wherein the third gate structure is electrically coupled to a second interconnect structure extending along the second lateral direction.
18. 18 . A semiconductor device, comprising: a first gate structure extending along a first lateral direction; a second gate structure extending along the first lateral direction and spaced from the first gate structure along a second lateral direction perpendicular to the first lateral direction; a source/drain structure interposed between the first gate structure and the second gate structure along the second lateral direction; a contact structure including a first portion and a second portion; and a first interconnect structure extending along the second lateral direction; wherein the contact structure is configured to electrically connect the first gate structure to the first interconnect structure, wherein the first portion of the contact structure is vertically disposed over the first gate structure with a first height, and wherein the second portion of the contact structure is vertically disposed over the source/drain structure with a second height higher than the first height.
19. 19 . The semiconductor device of claim 18 , wherein the first gate structure is connected only to the first portion of the contact structure, and the first interconnect structure is connected only to the second portion of the contact structure.
20. 20 . The semiconductor device of claim 18 , further comprising: a third gate structure extending along the first lateral direction, and disposed opposite the first gate structure from the second gate structure along the second lateral direction; wherein the third gate structure is electrically coupled to a second interconnect structure extending along the second lateral direction.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation application of U.S. patent application Ser. No. 18/604,071 filed on Mar. 13, 2024, which is a continuation application of U.S. patent application Ser. No. 17/835,281 filed on Jun. 8, 2022, which is a divisional application of U.S. patent application Ser. No. 16/803,497 filed on Feb. 27, 2020, each of which is incorporated by reference herein in its entirety. BACKGROUND The semiconductor integrated circuit (IC) industry has experienced exponential growth. In semiconductor IC design, standard cells methodologies are commonly used for the design of semiconductor devices on a chip. Standard cell methodologies use standard cells as abstract representations of certain functions to integrate millions, or billions, devices on a single chip. As ICs continue to scale down, more and more devices are integrated into the single chip. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 illustrates a cross-sectional view of an example semiconductor device including a recessed interconnect structure, in accordance with some embodiments. FIG. 2 illustrates a cross-sectional view of another example semiconductor device including a recessed interconnect structure, in accordance with some embodiments. FIG. 3 illustrates a circuit diagram of an example circuit, in accordance with some embodiments. FIG. 4 illustrates an example layout design of a standard cell representing the circuit of FIG. 3, in accordance with some embodiments. FIG. 5 illustrates a cross-sectional view of a semiconductor device, formed by at least a portion of the layout design of FIG. 4, that includes a recessed interconnect structure, in accordance with some embodiments. FIGS. 6A and 6B illustrate example layout designs of a standard cell representing the circuit of FIG. 3, in accordance with some embodiments. FIG. 7 illustrates a perspective view of a semiconductor device, formed by at least a portion of the layout designs of FIGS. 6A-B, that includes a recessed interconnect structure, in accordance with some embodiments. FIG. 8 illustrates a flowchart of a method of manufacturing a semiconductor device, in accordance with some embodiments. FIG. 9 illustrates a block diagram of a system of generating an IC layout design, in accordance with some embodiments. FIG. 10 illustrates a block diagram of an IC manufacturing system, and an IC manufacturing flow associated therewith, in accordance with some embodiments. FIG. 11 illustrates a flow chart of an example method for forming a semiconductor device including a recessed interconnect structure, in accordance with some embodiments. FIGS. 12A, 12B, 12C, 12D, 12E, 12F, 12G, 12H, 12I, 12J, 12K, 12L, and 12M illustrate cross-sectional views of an example semiconductor device during various fabrication stages, made by the method of FIG. 11, in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. With the tren