US-20260130203-A1 - SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

US20260130203A1US 20260130203 A1US20260130203 A1US 20260130203A1US-20260130203-A1

Abstract

A semiconductor structure is provided. The semiconductor structure includes a lower fin element, an isolation structure surrounding the lower fin element, and a functional circuit and an electrical connection structure. The functional circuit includes a set of nanostructures over the lower fin element, and a gate stack wrapping around the set of nanostructures. The electrical connection structure includes a through via embedded in the isolation structure, and a plurality of gate rails and a plurality of contact rails that are arranged horizontally in an alternating manner on the through via.

Inventors

Ta-Chun Lin
Chih-Hong Hwang
Jhon-Jhy Liaw

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260507
Application Date: 20241105

Claims (20)

1 . A method for forming a semiconductor structure, comprising: forming a plurality of gate rails over a first cell region of a substrate; forming a plurality of contact rails over the first cell region of the substrate, wherein the gate rails and the contact rails are alternatingly arranged; removing gate dielectric layers of the plurality of gate rails to expose gate electrode layers of the gate rails; and forming a through via under the plurality of gate rails and the plurality of contact rails.
2 . The method for forming the semiconductor structure as claimed in claim 1 , wherein the through via is in direct contact with the gate electrode layers of the gate rails and the plurality of contact rails.
3 . The method for forming the semiconductor structure as claimed in claim 1 , further comprising: forming an active region over the first cell region of the substrate; forming a plurality of gate stacks across the active region over the first cell region of the substrate; and cutting through the plurality of gate stacks into the plurality of gate rails using a gate-cut feature.
4 . The method for forming the semiconductor structure as claimed in claim 3 , wherein in a top view, the gate-cut feature partially overlaps the through via.
5 . The method for forming the semiconductor structure as claimed in claim 1 , wherein the through via includes a plurality of protrusions, and the protrusions of the through via extend from a sidewall of the through via and overlaps the respective contact rails.
6 . The method for forming the semiconductor structure as claimed in claim 1 , further comprising: forming an isolation structure over the substrate, wherein the plurality of gate rails and the plurality of contact rails are formed on the isolation structure; flipping the substrate; removing the substrate; etching the isolation structure to form a trench; and forming the through via in the trench.
7 . The method for forming the semiconductor structure as claimed in claim 6 , wherein during the etching of the isolation structure, the plurality of gate rails are etched at a first etching rate, and the plurality of contact rails are etched at a second etching rate that is slower than the first etching rate.
8 . The method for forming the semiconductor structure as claimed in claim 1 , further comprising: forming a set of nanostructures over a second cell region of the substrate; and forming a gate stack to surround the nanostructures, wherein the through via is electrically connected to the gate stack.
9 . The method for forming the semiconductor structure as claimed in claim 1 , further comprising: forming a set of nanostructures over a second cell region of the substrate; forming a source/drain feature adjoining the set of nanostructures; forming a backside via under the source/drain feature; and forming a power rail under and electrically connected to the backside via and the through via.
10 . The method for forming the semiconductor structure as claimed in claim 9 , wherein a cell height of the first cell region is twice a cell height of the second cell region.
11 . A method for forming a semiconductor structure, comprising: forming a first active region and a second active region over a substrate; forming an isolation structure surrounding lower portions of the first active region and the second active region; forming a gate electrode layer across the first active region, the second active region and the isolation structure; etching the isolation structure to form a trench between the first active region and the second active region, wherein the trench exposes a backside surface of the gate electrode layer; and forming a through via in the trench.
12 . The method for forming the semiconductor structure as claimed in claim 11 , further comprising: forming a first source/drain feature and a second source/drain feature on the first active region and the second active region, respectively; and forming a contact rail on the first source/drain feature and the second source/drain feature, wherein the trench further exposes a backside surface of the contact rail.
13 . The method for forming the semiconductor structure as claimed in claim 11 , further comprising: forming a first dummy gate structure, a second dummy gate structure and a third dummy gate structure across the first active region, the second active region and the isolation structure; replacing the first dummy gate structure and the third dummy gate structure with a first insulating strip and a second insulating strip, respectively; and replacing the second dummy gate structure with the gate electrode layer, wherein the gate electrode layer is located between the first insulating strip and the second insulating strip.
14 . The method for forming the semiconductor structure as claimed in claim 11 , wherein the trench exposes sidewalls of the gate electrode layer.
15 . The method for forming the semiconductor structure as claimed in claim 11 , further comprising: forming a stack of alternating first semiconductor layers and second semiconductor layers over the substrate; patterning the stack to form the first active region and the second active region; removing the first semiconductor layers of the first active region and the second active region, wherein the gate electrode layer surrounds the second semiconductor layers of the first active region and the second active region; and forming a first gate-cut feature and a second gate-cut feature through the gate electrode layer, wherein the trench exposes the first gate-cut feature and the second gate-cut feature.
16 . A semiconductor structure, comprising: a first lower fin element; an isolation structure surrounding the first lower fin element; a functional circuit, comprising: a first set of nanostructures over the first lower fin element; and a gate stack wrapping around the first set of nanostructures; and an electrical connection structure, comprising: a through via embedded in the isolation structure; and a plurality of gate rails and a plurality of contact rails arranged horizontally in an alternating manner on the through via.
17 . The semiconductor structure as claimed in claim 16 , further comprising: at least one insulating strip separating the electrical connection structure from the functional circuit, wherein the at least one insulating strip extends in a horizontal direction that is parallel to longitudinal axes of the plurality of gate rails.
18 . The semiconductor structure as claimed in claim 16 , wherein the electrical connection structure is electrically coupled to the functional circuit.
19 . The semiconductor structure as claimed in claim 16 , further comprising: a second lower fin element and a third lower fin element interposed by the through via of the electrical connection structure, wherein a width of the second lower fin element is thinner than a width of the first lower fin element.
20 . The semiconductor structure as claimed in claim 16 , wherein the electrical connection structure further comprises a via rail on and in direct contact with the plurality of gate rails and the plurality of contact rails.

Description

BACKGROUND The electronics industry is experiencing an ever-increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). So far, these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such miniaturization has introduced greater complexity into the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology. Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device that has been introduced is the gate-all around transistor (GAA). The GAA device gets its name from the gate structure, which can extend around the channel region and provide access to the channel on two or four sides. GAA devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, and their structure allows them to be aggressively scaled-down while maintaining gate control and mitigating SCEs. In conventional processes, GAA devices provide a channel in a silicon nanowire. However, integration of fabrication of the GAA features around the nanowire can be challenging. For example, while current methods have been satisfactory in many respects, continued improvements are still needed. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a perspective view of a semiconductor structure, in accordance with some embodiments of the disclosure. FIGS. 2A, 2C, 2E, 2F and 2I are layouts (top views) illustrating the formation of a semiconductor structure at various intermediate stages, in accordance with some embodiments of the disclosure. FIGS. 2A-1, 2A-2 and 2A-3 are cross-sectional views of the semiconductor structure at one of the intermediate stages corresponding to line X-X, line Y1-Y1 and line Y2-Y2 of FIG. 2A, in accordance with some embodiments of the disclosure. FIGS. 2B-1, 2B-2 and 2B-3 are cross-sectional views of the semiconductor structure at one of the intermediate stages corresponding to line X-X, line Y1-Y1 and line Y2-Y2 of FIG. 2A, in accordance with some embodiments of the disclosure. FIGS. 2C-1, 2C-2 and 2C-3 are cross-sectional views of the semiconductor structure at one of the intermediate stages corresponding to line X-X, line Y1-Y1 and line Y2-Y2 of FIG. 2C, in accordance with some embodiments of the disclosure. FIGS. 2D-1, 2D-2 and 2D-3 are cross-sectional views of the semiconductor structure at one of the intermediate stages corresponding to line X-X, line Y1-Y1 and line Y2-Y2 of FIG. 2C, in accordance with some embodiments of the disclosure. FIGS. 2E-1, 2E-2 and 2E-3 are cross-sectional views of the semiconductor structure at one of the intermediate stages corresponding to line X-X, line Y1-Y1 and line Y2-Y2 of FIG. 2E, in accordance with some embodiments of the disclosure. FIGS. 2F-1, 2F-2 and 2F-3 are cross-sectional views of the semiconductor structure at one of the intermediate stages corresponding to line X-X, line Y1-Y1 and line Y2-Y2 of FIG. 2F, in accordance with some embodiments of the disclosure. FIGS. 2G-1, 2G-2 and 2G-3 are cross-sectional views of the semiconductor structure at one of the intermediate stages corresponding to line X-X, line Y1-Y1 and line Y2-Y2 of FIG. 2F, in accordance with some embodiments of the disclosure. FIGS. 2H-1, 2H-2 and 2H-3 are cross-sectional views of the semiconductor structure at one of the intermediate stages corresponding to line X-X, line Y1-Y1 and line Y2-Y2 of FIG. 2F, in accordance with some embodiments of the disclosure. FIGS. 2I-1, 2I-2 and 2I-3 are cross-sectional views of the semiconductor structure at one of the intermediate stages corresponding to line X-X, line Y1-Y1 and line Y2-Y2 of FIG. 21, in accordance with some embodiments of the disclosure. FIGS. 3A and 3B are schematic views illustrating an electrical transmission route including an electrical connection cell region, in accordance with some embodiments of the disclosure. FIG. 4 is a layout (top view) illustrating a semiconductor structure, in accordance with some embodiments of the disclosure. FIGS. 4-1 and 4-2 are cross-sectio