US-20260130204-A1 - SEMICONDUCTOR DEVICE

US20260130204A1US 20260130204 A1US20260130204 A1US 20260130204A1US-20260130204-A1

Abstract

A semiconductor device includes: a substrate including an upper surface and a lower surface opposite to the upper surface; an active pattern disposed on the upper surface of the substrate and extending in a first direction; a field insulating film disposed on the upper surface of the substrate and covering a sidewall of the active pattern; a power rail disposed on the lower surface of the substrate and extending in the first direction; a trench formed in the substrate and exposing a portion of the power rail; and a metal pattern filling at least a portion of the trench and connected to the power rail, wherein a bottom surface of the trench is substantially coplanar with the lower surface of the substrate, wherein a sidewall of the trench has a convex shape, and wherein at least a portion of the field insulating film is disposed in the trench.

Inventors

Bo Ram Lee
Ki-II KIM

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20260105
Priority Date: 20221011

Claims (20)

1 . A semiconductor device, comprising: a power rail extending in a first direction; a metal pattern on the power rail; a power rail via on the metal pattern; a field insulating film on the metal pattern and on a sidewall of the power rail via; a gate electrode extending in a second direction intersecting the first direction; and a source/drain pattern on a side surface of the gate electrode; wherein the power rail via is electrically connected to the source/drain pattern and the power rail, and a sidewall of the metal pattern has a convex shape.
2 . The semiconductor device of claim 1 , further comprising: wherein a lowest point of the field insulating film is at a lower level than a highest point of the metal pattern.
3 . The semiconductor device of claim 1 , wherein a width, in the second direction, of the metal pattern gradually increases and then decreases in a third direction intersecting the first direction and the second direction.
4 . The semiconductor device of claim 1 , wherein an upper surface of the metal pattern is concave toward the power rail.
5 . The semiconductor device of claim 1 , wherein an upper surface of the metal pattern is convex toward the power rail via.
6 . The semiconductor device of claim 1 , wherein an interface between the field insulating film and the metal pattern is convex toward the power rail.
7 . The semiconductor device of claim 1 , wherein a lower portion of the power rail via overlaps the metal pattern in the second direction.
8 . The semiconductor device of claim 1 , wherein the power rail via partially overlaps the metal pattern in a third direction intersecting the first direction and the second direction.
9 . The semiconductor device of claim 1 , wherein the power rail via contacts an upper surface of the metal pattern and a sidewall of the metal pattern.
10 . The semiconductor device of claim 9 , wherein the power rail via further contacts an upper surface of the power rail.
11 . The semiconductor device of claim 1 , further comprising: a source/drain contact on the source/drain pattern, wherein a bottom surface of the source/drain contact contacts an upper surface of the power rail via.
12 . The semiconductor device of claim 1 , further comprising: a source/drain contact on the source/drain pattern; and a via plug on the source/drain contact and on the power rail via, wherein the power rail via electrically connected to the source/drain pattern through the via plug and the source/drain contact.
13 . A semiconductor device, comprising: a first gate electrode; a second gate electrode spaced apart from the first gate electrode in a first direction; a first source/drain pattern between the first gate electrode and the second gate electrode; a second source/drain pattern between the first gate electrode and the second gate electrode, the second source/drain pattern spaced apart from the first source/drain pattern in a second direction intersecting the first direction; a power rail; a metal pattern on the power rail; a power rail via on the metal pattern; wherein the power rail via is electrically connected to the first source/drain pattern and the power rail, and is between the first gate electrode and the second gate electrode and between the first source/drain pattern and the second source/drain pattern, and a sidewall of the metal pattern has a convex shape.
14 . The semiconductor device of claim 13 , wherein a width, in the second direction, of the metal pattern gradually increases and then decreases in a third direction intersecting the first direction and the second direction.
15 . The semiconductor device of claim 13 , wherein an upper surface of the metal pattern is concave toward the power rail.
16 . The semiconductor device of claim 13 , wherein an upper surface of the metal pattern is convex toward the power rail via.
17 . The semiconductor device of claim 1 , wherein a lower portion of the power rail via overlaps the metal pattern in the second direction.
18 . The semiconductor device of claim 1 , wherein the power rail via partially overlaps the metal pattern in a third direction intersecting the first direction and the second direction.
19 . A semiconductor device, comprising: a power rail extending in a first direction; a metal pattern on the power rail; a power rail via on the metal pattern; a field insulating film on the metal pattern and on a sidewall of the power rail via; a gate electrode extending in a second direction intersecting the first direction; a first source/drain pattern on a sidewall of the gate electrode; a second source/drain pattern on the sidewall of the gate electrode, the second source/drain pattern spaced apart from the first source/drain pattern in the second direction; and a lower insulating film on a sidewall of the power rail; wherein the power rail via is electrically connected to the source/drain pattern and the power rail, a sidewall of the metal pattern has a convex shape, and an interface of the metal pattern and the power rail is coplanar with an upper surface of the lower insulating film.
20 . The semiconductor device of claim 19 , wherein the metal pattern has a portion, wherein each of a width in the first direction of the portion of the metal pattern and a width in the second direction of the portion of the metal pattern gradually increases as the portion of the metal pattern extends in a third direction intersecting the first direction and the second direction.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a Continuation of U.S. patent application Ser. No. 18/219,140, filed on Jul. 7, 2023, which claims priority under 35 USC § 119 to Korean Patent Application No. 10-2022-0129805, filed on Oct. 11, 2022, and Korean Patent Application No. 10-2023-0024004, filed on Feb. 23, 2023 in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties. TECHNICAL FIELD The present inventive concept relates to a semiconductor device. DISCUSSION OF THE RELATED ART A scaling scheme for increasing an integration density of a semiconductor device proposes, generally, a multi-gate transistor in which a multi-channel active pattern (or a silicon body) in a shape of a fin or a nanowire is formed on a substrate, and a gate is formed on the multi-channel active pattern. Because such a multi-gate transistor uses a three-dimensional channel, the transistor may be easy to scale the same. Further, current control capability of the multi-gate transistor may be increased without increasing a gate length of the multi-gate transistor. In addition, the multi-gate transistor may effectively suppress SCE (short channel effect) in which potential of a channel area is affected by drain voltage. As a pitch size of the semiconductor device decreases, research is currently being conducted to reduce capacitance between contacts and to secure electrical stability in the semiconductor device. SUMMARY According to an embodiment of the present inventive concept, a semiconductor device includes: a substrate including an upper surface and a lower surface opposite to the upper surface; an active pattern disposed on the upper surface of the substrate and extending in a first direction; a field insulating film disposed on the upper surface of the substrate and covering a sidewall of the active pattern; a power rail disposed on the lower surface of the substrate and extending in the first direction; a trench formed in the substrate and exposing a portion of the power rail; and a metal pattern filling at least a portion of the trench and connected to the power rail, wherein a bottom surface of the trench is substantially coplanar with the lower surface of the substrate, wherein a sidewall of the trench has a convex shape, and wherein at least a portion of the field insulating film is disposed in the trench. According to an embodiment of the present inventive concept, a semiconductor device includes: a substrate including an upper surface and a lower surface opposite to the upper surface; an active pattern disposed on the upper surface of the substrate and extending in a first direction; a gate electrode covering at least a portion of the active pattern and extending in a second direction interesting the first direction; a power rail disposed on the lower surface of the substrate and extending in the first direction; a metal pattern disposed in the substrate and connected to the power rail; and a power rail via disposed on the metal pattern and disposed on one side of the gate electrode, wherein the power rail via is connected to the power rail via the metal pattern, wherein a bottom surface of the metal pattern extends in a parallel to the lower surface of the substrate and is substantially coplanar with the lower surface of the substrate, and wherein the metal pattern has a portion, wherein each of a width in the second direction of the portion of the metal pattern and a width in the first direction of the portion of the metal pattern gradually increases as the portion of the metal pattern extends in a direction from the lower surface of the substrate to the upper surface of the substrate. According to an embodiment of the present inventive concept, a semiconductor device includes: a substrate including an upper surface and a lower surface opposite to the upper surface; an active pattern disposed on the upper surface of the substrate and extending in a first direction; a gate electrode covering at least a portion of the active pattern and extending in a second direction intersecting the first direction; a field insulating film disposed on the upper surface of the substrate and covering a sidewall of the active pattern; a power rail disposed on the lower surface of the substrate and extending in the first direction; a trench formed in the substrate and exposing a portion of the power rail, wherein the trench has a convexly shaped sidewall; a metal pattern filling at least a portion of the trench and connected to the power rail; a source/drain pattern disposed on the active pattern and on one side of the gate electrode; a source/drain contact disposed on the source/drain pattern; and a power rail via disposed on the metal pattern and disposed on one side of the gate electrode, wherein the power rail via is connected to the power rail via the metal pattern, wherein a bottom surface of the trench is substantially coplanar with the lower surface