US-20260130205-A1 - SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME

US20260130205A1US 20260130205 A1US20260130205 A1US 20260130205A1US-20260130205-A1

Abstract

Provided are a semiconductor structure and a method for forming the same. The semiconductor structure includes a substrate, a signal line located on the substrate, and a contact structure extending along a first direction. The contact structure is disposed partially around an end part of the signal line, the contact structure is in contact with and electrically connected to the signal line, and the first direction is perpendicular to a top surface of the substrate.

Inventors

Chih-Cheng Liu

Assignees

CXMT Corporation

Dates

Publication Date: 20260507
Application Date: 20251107
Priority Date: 20230524

Claims (18)

1 . A semiconductor structure, comprising: a substrate; a signal line located on the substrate; and a contact structure extending along a first direction, wherein contact structure is disposed partially around an end part of the signal line, the contact structure is in contact with and electrically connected to the signal line, and the first direction is perpendicular to a top surface of the substrate.
2 . The semiconductor structure according to claim 1 , wherein the signal line extends along a second direction, and the second direction is parallel to the top surface of the substrate; the contact structure covers a top surface of the signal line and is disposed around part of a side wall of the signal line.
3 . The semiconductor structure according to claim 2 , wherein a width of the contact structure located on the top surface of the signal line along a third direction is a first width, a width of the signal line along the third direction is a second width, the first width is greater than or equal to the second width, the third direction is parallel to the top surface of the substrate, and the second direction intersects with the third direction.
4 . The semiconductor structure according to claim 3 , wherein the contact structure comprises: a main body portion located on the signal line and being in contact with and electrically connected to the signal line; and an extension portion disposed at an end part of the main body portion along the third direction and being in contact with and electrically connected to the main body portion, wherein the extension portion covers the side wall of the signal line.
5 . The semiconductor structure according to claim 4 , wherein a plurality of extension portions are spaced apart along the second direction, and are all in contact with and electrically connected to the main body portion; the plurality of extension portions are disposed on two opposite sides of the main body portion along the third direction.
6 . The semiconductor structure according to claim 2 , wherein the contact structure comprises: a main body portion located on the signal line and being in contact with and electrically connected to the signal line; and an extension portion disposed at an end part of the main body portion along the second direction and being in contact with and electrically connected to the main body portion, wherein the extension portion covers an end surface of the signal line.
7 . The semiconductor structure according to claim 3 , wherein a plurality of signal lines are spaced apart along the third direction, a plurality of contact structures are electrically connected to the plurality of signal lines in a one-to-one correspondence, and each of the plurality of contact structures is disposed partially around an end part of the signal line electrically connected thereto; two of the plurality of contact structures electrically connected to two adjacent signal lines are staggered along the third direction.
8 . The semiconductor structure according to claim 7 , wherein the plurality of signal lines are sequentially arranged in the third direction, and the contact structure electrically connected to an odd-numbered signal line and the contact structure electrically connected to an even-numbered signal line are disposed opposite to each other along the second direction.
9 . The semiconductor structure according to claim 2 , wherein in the first direction, a bottom surface of the contact structure is located below a bottom surface of the signal line.
10 . The semiconductor structure according to claim 1 , wherein the substrate further comprises therein an active region and an isolation region located outside the active region; the contact structure extends to inside of the isolation region along the first direction.
11 . The semiconductor structure according to claim 10 , wherein a depth of the isolation region inside the substrate along the first direction is a first depth, a depth of the contact structure extending to the isolation region along the first direction is a second depth, and the second depth is less than the first depth.
12 . A method for forming a semiconductor structure, comprising: providing a substrate; forming a signal line on the substrate; and forming a contact structure extending along a first direction, wherein the contact structure is partially disposed around an end part of the signal line, the contact structure is in contact with and electrically connected to the signal line, and the first direction is perpendicular to a top surface of the substrate.
13 . The method for forming a semiconductor structure according to claim 12 , wherein specific steps of forming the contact structure extending along the first direction ctheomprise: forming an insulating layer covering the signal line; etching the insulating layer to form a contact groove exposing at least the signal line; and forming, in the contact groove, the contact structure in contact with and electrically connected to the signal line exposed.
14 . The method for forming a semiconductor structure according to claim 13 , wherein the substrate further comprises therein an active region and an isolation region located outside the active region; a specific step of forming the contact groove exposing at least the signal line comprises: etching the insulating layer using the signal line as an etching stop layer and over-etching the isolation region to form the contact groove at least extending to inside of the isolation region along the first direction.
15 . The method for forming a semiconductor structure according to claim 13 , wherein the signal line extends along a second direction, and the second direction is parallel to the top surface of the substrate; a specific step of forming the contact groove exposing at least the signal line comprises: etching the insulating layer to form a first etched groove exposing a top surface of the signal line and a second etched groove exposing a side wall of the signal line, wherein the first etched groove is in communication with the second etched groove, a plurality of second etched grooves are disposed on two opposite sides of the first etched groove along a third direction, the first etched groove and the plurality of second etched grooves jointly form the contact groove, the third direction is parallel to the top surface of the substrate, and the second direction intersects with the third direction.
16 . The method for forming a semiconductor structure according to claim 14 , wherein a depth of the isolation region inside the substrate along the first direction is a first depth, and a depth of the contact groove extending to the isolation region is less than or equal to a quarter of the first depth.
17 . The method for forming a semiconductor structure according to claim 14 , further comprising: forming, on a top surface of the contact structure, an interconnect metal layer electrically connected to the contact structure, wherein a width of the interconnect metal layer is less than a width of the top surface of the contact structure.
18 . The method for forming a semiconductor structure according to claim 17 , further comprising: forming a cap layer covering the contact structure and the insulating layer after forming the contact structure.

Description

The present application is a continuation of International Patent Application No. PCT/CN2024/089972, filed on Apr. 26, 2024, which claims priority to Chinese Patent Application No. 202310613877.7 filed with China National Intellectual Property Administration on May 24, 2023 and entitled “SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME”, the content of which is incorporated herein by reference in their entireties. TECHNICAL FIELD The present disclosure relates to the technical field of semiconductor manufacturing, and particularly, to a semiconductor structure and a method for forming the same. BACKGROUND A dynamic random access memory (DRAM) is a commonly used semiconductor apparatus in electronic devices, such as computers. It is composed of a plurality of memory cells, and each memory cell typically includes a transistor and a capacitor. A gate of the transistor is electrically connected to a word line, a source of the transistor is electrically connected to a bit line, and a drain of the transistor is electrically connected to a capacitor. The word line voltage on the word line can control switching-on/off of the transistor, such that data information stored in the capacitor can be read from the capacitor via the bit line, or data information can be written into the capacitor via the bit line. In a semiconductor structure (such as a DRAM), a signal line, such as a word line or a bit line needs to be led out via a contact structure so as to facilitate electrical connection with an external control circuit. The contact structure is usually landed on the top surface of a signal line, such as a word line or a bit line. However, as the size of the semiconductor structure, such as the DRAM, continues to shrink, the contact area between the contact structure and the signal line, such as the word line and the bit line, continues to decrease, such that the contact resistance between the contact structure and the signal line greatly increases, thereby reducing the performance of the semiconductor structure. Therefore, how to reduce the contact resistance inside the semiconductor structure and thus improve the performance of the semiconductor structure is an urgent technical problem to be solved at present. SUMMARY Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same. According to some embodiments, the present disclosure provides a semiconductor structure. The semiconductor structure includes: a substrate; a signal line located on the substrate; and a contact structure extending along a first direction, where the contact structure is disposed partially around an end part of the signal line, the contact structure is in contact with and electrically connected to the signal line, and the first direction is perpendicular to a top surface of the substrate. According to some other embodiments, the present disclosure further provides a method for forming a semiconductor structure. The method includes the following steps: providing a substrate; forming a signal line on the substrate; and forming a contact structure extending along a first direction, where the contact structure is disposed partially around an end part of the signal line, the contact structure is in contact with and electrically connected to the signal line, and the first direction is perpendicular to a top surface of the substrate. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a schematic top view of a semiconductor structure according to an embodiment of the present disclosure; FIG. 2 is a schematic cross-sectional view taken along line A-A in FIG. 1; FIG. 3 is a schematic cross-sectional view taken along line B-B in FIG. 1; FIG. 4 is a schematic diagram of a positional relationship between part of a contact structure and a signal line according to an embodiment of the present disclosure, the part of the contact structure being disposed around a side wall of the signal line; FIG. 5 is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure; FIG. 6, FIG. 7, FIG. 8 and FIG. 9 are schematic diagrams of main process structures in a process of forming a semiconductor structure according to an embodiment of the present disclosure; and FIG. 10, FIG. 11, FIG. 12 and FIG. 13 are schematic diagrams of various positional relationships between a contact structure and a signal line according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS Embodiments of the semiconductor structure and the method for forming the same provided by the present disclosure will be described in detail below with reference to the accompanying drawings. Embodiments of the present disclosure provide a semiconductor structure. FIG. 1 is a schematic top view of a semiconductor structure according to an embodiment of the present disclosure, FIG. 2 is a schematic cross-sectional view taken along line A-A in FIG. 1, and FIG. 3 is a schematic cross-