US-20260130206-A1 - METAL INTERCONNECT STRUCTURES AND METHODS THEREOF

Abstract

A semiconductor device includes a plurality of metallization layers vertically disposed with respect to and electrically couple to a plurality of transistors. Each of the plurality of metallization layers includes a metal line and a metal via. Each of the metal lines and the metal vias are coupled to a barrier layer. The metal lines and the metal vias each essentially consist of a first material comprising copper (Cu), silver (Ag), and carbon (C). The barrier layer essentially consists of a second material including zirconium nitride (ZrN).

Inventors

• Eric Paul Young
• Li-Hsin CHU
• Wen-Chih Chiang
• Yung-Lung Hsu

Assignees

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date

20260507

Application Date

20241107

Claims (20)

1. 1 . A semiconductor device, comprising: a plurality of metallization layers vertically disposed with respect to and electrically coupled to a plurality of transistors, each of the plurality of metallization layers comprising a metal line and a metal via electrically coupled to each other, and each of the metal lines and the metal vias are coupled to a barrier layer, wherein the metal lines and the metal vias each essentially consist of a first material comprising copper (Cu), silver (Ag), and carbon (C), and wherein the barrier layer essentially consists of a second material comprising zirconium nitride (ZrN).
2. 2 . The semiconductor device of claim 1 , wherein a ratio of an amount of silver in the first material to a total amount of the first material in mass is greater than 30%.
3. 3 . The semiconductor device of claim 1 , wherein a ratio of an amount of silver in the first material to a total amount of the first material in mass is greater than 35%.
4. 4 . The semiconductor device of claim 1 , wherein a ratio of an amount of carbon in the first material to a total amount of the first material in mass is in a range from 3% to 10%.
5. 5 . The semiconductor device of claim 1 , wherein a ratio of an amount of carbon in the first material to a total amount of the first material in mass is in a range from 5% to 8%.
6. 6 . The semiconductor device of claim 1 , wherein a bottom-most via in a bottom-most metallization layer of the plurality of metallization layers is electrically coupled to one of the plurality of transistors through a metal contact made of a third material.
7. 7 . The semiconductor device of claim 6 , wherein the third material comprises tungsten (W).
8. 8 . The semiconductor device of claim 1 , further comprising a redistribution layer (RDL) disposed over the plurality of metallization layers, and coupled to a top-most metallization layer of the plurality of metallization layers.
9. 9 . The semiconductor device of claim 8 , wherein the redistribution layer is made of a fourth material (AlSiCu) comprising aluminum (Al), silicon (Si), and copper (Cu).
10. 10 . A semiconductor device, comprising: a plurality of metallization layers vertically disposed with respect to and electrically coupled to a transistor formed on a substrate, each of the plurality of metallization layers comprising a metal line and a metal via electrically coupled to each other, wherein the metal line and the metal via each essentially consist of a first material comprising copper (Cu), silver (Ag), and carbon (C).
11. 11 . The semiconductor device of claim 10 , wherein each of the metal lines and the metal vias are at least partially surrounded at a bottom surface and sidewalls thereof by a barrier layer.
12. 12 . The semiconductor device of claim 11 , wherein the barrier layer is made of a second material comprising zirconium nitride (ZrN).
13. 13 . The semiconductor device of claim 10 , wherein a ratio of an amount of silver in the first material to a total amount of the first material in mass is greater than 30%.
14. 14 . The semiconductor device of claim 10 , wherein a ratio of an amount of carbon in the first material to a total amount of the first material in mass is in a range from 3% to 10%.
15. 15 . A method of manufacturing a semiconductor device, comprising: forming a first metallization layer of a plurality of metallization layers disposed vertically respect to a substrate; forming a first metal line in the first metallization layer; forming a first metal via over the first metal line in the first metallization layer; forming a second metallization layer of the plurality of metallization layers over the first metallization layer; forming a second metal line in the second metallization layer; and forming a second metal via over the second metal line in the second metallization layer, wherein the first metal line, the first metal via, the second metal line, and the second metal via each essentially consist of a first material comprising copper (Cu), silver (Ag), and carbon (C).
16. 16 . The method of claim 15 , wherein the first metal line is electrically coupled to the first metal via, wherein the second metal line is electrically coupled to the first metal via, and wherein the second metal via is electrically coupled to the second metal line.
17. 17 . The method of claim 15 , wherein a ratio of an amount of silver in the first material to a total amount in the first material in mass is greater than 30%.
18. 18 . The method of claim 15 , wherein a ratio of an amount of carbon in the first material to a total amount of the first material in mass is in a range from 3% to 10%.
19. 19 . The method of claim 15 , further comprising: forming a first line barrier layer coupled to the first metal line at a bottom surface and sidewalls of the first metal line in the first metallization layer, posting forming the first metal line; forming a first via barrier layer coupled to the first metal via at a bottom surface and sidewalls of the first metal via in the first metallization layer, posting forming the first metal via; forming a second line barrier layer coupled to the second metal line at a bottom surface and sidewalls of the second metal line in the second metallization layer, posting forming the second metal line; and forming a second via barrier layer coupled to the second metal via at a bottom surface and sidewalls of the second metal via in the second metallization layer, posting forming the second metal via.
20. 20 . The method of claim 19 , wherein the first line barrier layer, the first via barrier layer, the second line barrier layer, and the second via barrier layer are made of a second material comprising zirconium nitride (ZrN).

Description

BACKGROUND The semiconductor industry has experienced rapid growth due to continuous improvements in integration density of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size (e.g., shrinking the semiconductor process node towards the sub-20 nm node), which allows more components to be integrated into a given area. With further technology developments in many areas like Artificial Intelligence (AI), more metal layers are required in semiconductor devices to support high computational requirements. However, increased number of metal layers in semiconductor devices may cause increased overall signal Resistance-Capacitance (RC) time delay, and thus may disadvantageously impact product performance. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is an example cross-sectional view of a semiconductor device including a large number of metal interconnect structures in accordance with some embodiments. FIG. 2 is an example flow chart of a method for fabricating a semiconductor device including a large number of metal interconnect structures in accordance with some embodiments. FIGS. 3, 4, 5, 6, 7 and 8 illustrate cross-sectional views of an example semiconductor device, during various fabrication stages, made by the method of FIG. 2 in accordance with some embodiments. FIG. 9 are example chart diagrams illustrating impact of Resistance-Capacitance (RC) time delay on product performance of a semiconductor device. FIG. 10 is an example diagram illustrating different overall via resistance performances of different example materials. FIG. 11 is an example diagram illustrating different anti-permeation performances of different example materials. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over, or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” “top,” “bottom” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. The semiconductor industry has experienced rapid growth due to continuous improvements in integration density of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For example, back-end technologies begin with contact (e.g., W) connected to silicided front-end gate, source, and/or drain electrodes. These connections may be linked to e.g., silicided silicon first and then link to metal-gates or may be linked directly to metal-gates. Further inter-metal connections of a metal (e.g., Cu) with different thicknesses may be stacked until a pad of a material such as aluminum copper (AlCu) for far back-end bumping processes. With further technology developments in many areas like Artificial Intelligence (AI), more metal layers (or metallization layers) are required in semiconductor devices to support high computational requirements. However, increased number of metal layers in semiconductor devices may cause increased overall signal Resistance-Capacitance (RC) time delay, and thus may disadvantageously impact product performance of semiconductor devices. The present disclosure provides various embodiments of a semiconductor device. In some embodiments, the sem