US-20260130207-A1 - SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

US20260130207A1US 20260130207 A1US20260130207 A1US 20260130207A1US-20260130207-A1

Abstract

A semiconductor device includes: an active region having a semiconductor element and a surface electrode provided by a wiring electrode material and connected to the semiconductor element on a side adjacent to a surface of a semiconductor chip; and a pad arrangement region having a pad provided by the wiring electrode material. The pad arrangement region overlaps the active region in a direction normal to the surface of the semiconductor chip. In a part where the pad arrangement region and the active region overlap, the pad is disposed on the surface electrode through an isolation insulating film so that the wiring electrode material is in two layers to provide a double-layer wiring electrode structure. In a part of the active region without overlapping the pad arrangement region, the surface electrode has a single-layer wiring electrode structure composed of a single layer of the wiring electrode material.

Inventors

Masato Noborio
Yoshitaka Kato
Takeshi Endo

Assignees

DENSO CORPORATION
TOYOTA JIDOSHA KABUSHIKI KAISHA
MIRISE Technologies Corporation

Dates

Publication Date: 20260507
Application Date: 20251230
Priority Date: 20210929

Claims (19)

1 . A semiconductor device provided by a semiconductor chip, the semiconductor device comprising: an active region having a semiconductor element and a surface electrode, the surface electrode including a first-layer wiring electrode made of a wiring electrode material, connected to the semiconductor element, and disposed on a surface of the semiconductor chip, the first-layer wiring electrode being in a first layer on an interlayer insulating film; and a pad arrangement region having a pad, the pad composed of a second-layer wiring electrode made of the wiring electrode material, the second-layer wiring electrode being in a second layer above the first layer, wherein the pad arrangement region is disposed to overlap the active region in a direction normal to the surface of the semiconductor chip, the second-layer wiring electrode forming the pad is disposed above the first-layer wiring electrode of the surface electrode through an isolation insulating film so that the wiring electrode material is in two layers to provide a double-layer wiring electrode structure, the pad is electrically insulated from the surface electrode through the isolation insulating film in the pad arrangement region, in a part of the active region without overlapping with the pad arrangement region, the surface electrode has a surface exposed from an opening of a passivation film disposed at the surface of the semiconductor chip, the exposed top surface of the surface electrode, as the source electrode, provides an electrode pad surface, in the pad arrangement region, the pad has a single-layer wiring electrode structure composed of the second-layer wiring electrode and has a second surface exposed from a pad opening of the passivation film, the surface electrode extends over an entire bottom side of the pad in the pad arrangement region, the semiconductor element includes a contact region, the semiconductor device further comprising: a wiring layer disposed outside the double-layer wiring electrode structure, and electrically connected to the contact region, and the wiring layer has a single-layer wiring electrode structure composed of a single layer of the wiring electrode material.
2 . The semiconductor device according to claim 1 , wherein the contact region extends to a position below the wiring layer, the single layer forming the wiring layer is the first-layer wiring electrode in the first layer on the interlayer insulating film, and is in contact with the contact region through a contact hole formed in the interlayer insulating film.
3 . The semiconductor device according to claim 1 , wherein a total area of one or more regions having the double-layer wiring electrode structure is 30% or less of an area of the active region.
4 . The semiconductor device according to claim 1 , wherein each of the surface electrode and the pad is line symmetrical, as seen from a plan view, with respect to a straight line that is a center line of the semiconductor chip passing through a center of the surface electrode.
5 . The semiconductor device according to claim 1 , wherein the number of pads is five or fewer.
6 . The semiconductor device according to claim 1 , wherein the isolation insulating film is a silicon oxide film.
7 . The semiconductor device according to claim 1 , wherein the isolation insulating film is a silicon nitride film.
8 . The semiconductor device according to claim 1 , wherein the wiring electrode material is made of AlSi.
9 . The semiconductor device according to claim 1 , wherein the semiconductor chip includes a semiconductor substrate made of silicon carbide, and the semiconductor element is provided in the semiconductor substrate.
10 . The semiconductor device according to claim 9 , wherein the semiconductor substrate made of silicon carbide is n + -type.
11 . The semiconductor device according to claim 1 , wherein the semiconductor element is a vertical MOSFET.
12 . The semiconductor device according to claim 1 , wherein the semiconductor element is a vertical IGBT.
13 . The semiconductor device according to claim 1 , wherein from a plan view, the semiconductor chip has a rectangular plate shape.
14 . The semiconductor device according to claim 1 , wherein the wiring layer having the single-layer wiring electrode structure is a hole extracting layer connected to the source electrode through the contact region.
15 . A power module, comprising: the semiconductor device according to claim 1 ; a first heat sink; a second heat sink; and a resin mold, wherein: the power module functions as a switching element to drive a motor, an upper surface of the semiconductor device is joined, via a joining material, to a lower surface of the first heat sink, a lower surface of the semiconductor device is joined, via the joining material, to an upper surface of the second heat sink, the resin mold encapsulates the semiconductor device, the first heat sink, and the second heat sink.
16 . The power module according to claim 15 , wherein each of the first heat sink and the second heat sink comprises a top metal layer, an insulating layer, and a bottom metal layer, stacked in that order such that the insulating layer is disposed between the top metal layer and the bottom metal layer.
17 . The power module according to claim 16 , wherein the bottom metal layer of the first heat sink is divided into a plurality of connecting portions that form the lower surface of the first heat sink.
18 . The power module according to claim 17 , wherein one of the plurality of connecting portions is connected to the electrode pad surface of the source electrode, and at least another of the plurality of connecting portions is connected to the pad in the pad arrangement region.
19 . A semiconductor device provided by a semiconductor chip, the semiconductor device comprising: an active region having a semiconductor element and a surface electrode, the surface electrode including a first-layer wiring electrode made of a wiring electrode material, connected to the semiconductor element, and disposed on a surface of the semiconductor chip, the first-layer wiring electrode being in a first layer on an interlayer insulating film; a pad arrangement region having a pad, the pad composed of a second-layer wiring electrode made of the wiring electrode material, the second-layer wiring electrode being in a second layer above the first layer, wherein the pad arrangement region is disposed to overlap the active region in a direction normal to the surface of the semiconductor chip, the second-layer wiring electrode forming the pad is disposed above the first-layer wiring electrode of the surface electrode through an isolation insulating film so that the wiring electrode material is in two layers to provide a double-layer wiring electrode structure, the pad is electrically insulated from the surface electrode through the isolation insulating film in the pad arrangement region, in a part of the active region without overlapping with the pad arrangement region, the surface electrode has a surface exposed from an opening of a passivation film disposed at the surface of the semiconductor chip, the exposed top surface of the surface electrode, as the source electrode, provides an electrode pad surface, in the pad arrangement region, the pad has a single-layer wiring electrode structure composed of the second-layer wiring electrode and has a second surface exposed from a pad opening of the passivation film, the surface electrode extends over an entire bottom side of the pad in the pad arrangement region, the semiconductor element includes a contact region, the semiconductor device further comprising: a connecting region on a periphery of the active region, wherein the connecting region includes a hole extracting layer electrically connected to the source electrode through the contact region, the hole extracting layer has a single-layer wiring electrode structure composed of the first-layer wiring electrode in the first layer on the interlayer insulating film, and connected to the contact region through a contact hole formed in the interlayer insulating film.

Description

CROSS REFERENCE TO RELATED APPLICATIONS The present application is a continuation of U.S. Utility application Ser. No. 17/946,501 filed on Sep. 16, 2022 which claims the benefit of priority from Japanese Patent Application No. 2021-159834 filed on Sep. 29, 2021. The entire disclosures of the above applications are incorporated herein by reference in their entirety. TECHNICAL FIELD The present disclosure relates to a semiconductor device having a pad on a surface of a semiconductor chip, and a method for manufacturing the semiconductor device. BACKGROUND There is a semiconductor device in which a semiconductor element such as a switching element is formed in a semiconductor chip. In such a semiconductor device, an active region operated as a semiconductor element may be arranged over a wide range including the center of the semiconductor chip. A region of the semiconductor chip different from the active region, specifically, a region adjacent to the active region and along one side of the semiconductor chip may be used as a pad arrangement region in which pads are arranged. SUMMARY The present disclosure describes a semiconductor device having an active region and a pad arrangement region overlapping the active region, and a method for manufacturing the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS Objects, features and advantages of the present disclosure will become more apparent from the following detailed description made with reference to the accompanying drawings. in which: FIG. 1 is a cross-sectional view of a power module according to a first embodiment; FIG. 2A is a top layout view of a semiconductor chip provided in the power module shown in FIG. 1; FIG. 2B is a top layout view of a semiconductor chip in which a region having a double-layer wiring electrode structure is shown with hatching; FIG. 3 is a cross-sectional view taken along a line III-III in FIG. 2A in a configuration where a vertical MOSFET is formed in the semiconductor chip; FIG. 4 is a cross-sectional view taken along a line IV-IV in FIG. 2A in the configuration where the vertical MOSFET is formed in the semiconductor chip; FIG. 5 is a cross-sectional view of a semiconductor chip as a comparative example, corresponding to the cross-sectional view taken along the line III-III in FIG. 2A; FIG. 6 is a cross-sectional view of the semiconductor chip as the comparative example, corresponding to the cross-sectional view taken along the line IV-IV in FIG. 2A; FIG. 7 is a diagram showing simulation results of the on-resistances of the semiconductor chips of the first embodiment and the comparative example; FIG. 8 is a flow chart showing a method for manufacturing a semiconductor device; FIG. 9 is a top layout view of a semiconductor chip in which a region having a double-layer wiring electrode structure is shown with hatching; FIG. 10 is a cross-sectional view of a semiconductor chip according to a second embodiment, corresponding to the cross-sectional view taken along the line III-III in FIG. 2A; FIG. 11 is a top layout view of a semiconductor chip according to a fourth embodiment; and FIG. 12 is a top layout view of a semiconductor chip according to a fifth embodiment. DETAILED DESCRIPTION In such a semiconductor device, for example, an active region operated as a semiconductor element may be arranged over a wide range including the center of the semiconductor chip. A region of the semiconductor chip different from the active region, specifically, a region adjacent to the active region and along one side of the semiconductor chip may be used as a pad arrangement region in which pads are arranged. In the semiconductor device described above, since the active region and the pad arrangement region are separate regions, the pad arrangement region is a region that cannot contribute to operate the switching element. As a result, the ratio of the active region to a total area of the semiconductor chip is reduced due to the area of the pad arrangement region, and it is thus difficult to lower an on-resistance of the semiconductor element small enough. Therefore, the inventors of the present disclosure have found a structure in which the active region is expanded to a region below the pad in the pad arrangement region so that the region below the pas is also used as the active region. With such a configuration, the ratio of the active region to the total area of the semiconductor chip can be increased, and the on-resistance of the semiconductor element can be lowered. In the semiconductor device having such a structure, a semiconductor element is formed in a region below the pad arrangement region. Therefore, a wiring electrode material for forming the pad is arranged on a wiring electrode material for forming an electrode connected to the semiconductor element in an overlapping manner. That is, a wiring electrode connected to the semiconductor element is disposed as a lower layer wiring electrode in a first layer, and an upper layer wiri